Towards Faster Data Transfer by Spoof Plasmonics

With the emergence of complex architectures in modern electronics such as multi-chip modules, the increasing electromagnetic cross-talk in the circuitry causes a serious issue for high-speed, reliable data transfer among the chips. This thesis aims at developing a cross-talk resilient communication technology by utilizing a special form of electromagnetic mode, called spoof surface plasmon polariton for information transfer. The technique is based on the fact that a metal wire with periodic sub-wavelength patterns can support the propagation of confined electromagnetic mode, which can suppress cross-talk noise among the adjacent channels; and thus outperform conventional electrical interconnects in a parallel, high channel density data-bus. My developed model shows that, with 1 THz carrier frequency, the optimal design of cross-talk resilient spoof plasmon data-bus would allow each channel to support as high as 300 Gbps data, the bandwidth density can reach 1 Tbps per millimeter width of data-bus, and the digital pulse modulated carrier can travel more than 5 mm distance on the substrate. I have demonstrated that spoof plasmonic interconnects, comprised of patterned metallic conductors, can simultaneously accommodate electronic TEM mode, which is superior in cross-talk suppression at low-frequencies; and spoof plasmon mode, which is superior at high-frequencies. The research work is divided into two complementary parts: developing a theory for electromagnetic property analysis of spoof plasmon waveguide, and manipulating these properties for high-speed data transfer. Based on the theory developed, I investigated the complex interplay among various figure-of-merits of data transfer in spoof plasmonics, such as bandwidth density, propagation loss, thermal noise, speed of modulation, etc. My developed model predicts that with the availability of 1 THz carrier, the bit-error-rate of spoof plasmon data bus, subject to thermal noise would be $sim10^{-8}$ while the Shannon information capacity of the bus would be $10$ Tbps/mm. The model also predicts that, by proper designing of the modulator, it can be possible to alter the transmission property of the waveguide over one-fifth ($1/5$) of the spoof plasmon band which spans from DC frequency to the frequency of spoof plasmon resonance. To exemplify, if the spoof plasmon resonance is set at $1$ THz, then we can achieve more than $200$ Gbps speed of modulation with a very high extinction ratio, assuming the switching latency of the transistors at our disposal is negligible to the time-resolution of interest. We envision spoof plasmonic interconnects to constitute the next generation communication technology that will be transferring data at hundreds of Gigabit per second (Gbps) speed among different chips on a multi-chip module (MCM) carrier or system-on-chip (SoC) packaging.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/163041/1/srjoy_1.pd

Millimeter-Wave Band Pass Distributed Amplifier for Low-Cost Active Multi-Beam Antennas

Recently, there have been a great interest in the millimeter-wave (mmW) and terahertz (THz) bands due to the unique features they provide for various applications. For example, the mmW is not significantly affected by the atmospheric constraints and it can penetrate through clothing and other dielectric materials. Therefore, it is suitable for a vast range of imaging applications such as vision, safety, health, environmental studies, security and non-destructive testing. Millimeter-wave imaging systems have been conventionally used for high end applications implementing sophisticated and expensive technologies. Recent advancements in the silicon integrated and low loss material passive technologies have created a great opportunity to study the feasibility of low cost mmW imaging systems. However, there are several challenges to be addressed first. Examples are modeling of active and passive devices and their low performance, highly attenuated channel and poor signal to noise ratio in the mmW. The main objective of this thesis is to investigate and develop new technologies enabling cost-effective implementation of mmW and sub-mmW imaging systems. To achieve this goal, an integrated active Rotman lens architecture is proposed as an ultimate solution to combine the unique properties of a Rotman lens with the superiority of CMOS technology for fabrication of cost effective integrated mmW systems. However, due to the limited sensitivity of on-chip detectors in the mmW, a large number of high gain, wide-band and miniaturized mmW Low Noise Amplifiers (LNA) are required to implement the proposed integrated Rotman lens architecture. A unique solution presented in this thesis is the novel Band Pass Distributed Amplifier (BPDA) topology. In this new topology, by short circuiting the line terminations in a Conventional Distributed Amplifier (CDA), standing waves are created in its artificial transmission lines. Conventionally, standing waves are strongly avoided by carefully matching these lines to 50 Ω in order to prevent instability of the amplifier. This causes that a large portion of the signal be absorbed in these resistive terminations. In this thesis, it is shown that due to presence of highly lossy parasitics of CMOS transistor at the mmW the amplifier stability is inherently achieved. Moreover, by eliminating these lossy and noise terminations in the CDA, the amplifier gain is boosted and its noise figure is reduced. In addition, a considerable decrease in the number of elements enables low power realization of many amplifiers in a small chip area. Using the lumped element model of the transistor, the transfer function of a single stage BPDAs is derived and compared to its conventional counter part. A methodology to design a single stage BPDA to achieve all the design goals is presented. Using the presented design guidelines, amplifiers for different mmW frequencies have been designed, fabricated and tested. Using only 4 transistors, a 60 GHz amplifier is fabricated on a very small chip area of 0.105 mm2 by a low-cost 130 nm CMOS technology. A peak gain of 14.7 dB and a noise figure of 6 dB are measured for this fabricated amplifier. oreover, it is shown that by further circuit optimization, high gain amplification can be realized at frequencies above the cut-off frequency of the transistor. Simulations show 32 and 28 dB gain can be obtained by implementing only 6 transistors using this CMOS technology at 60 and 77 GHz. A 4-stage 85 GHz amplifier is also designed and fabricated and a measured gain of 10 dB at 82 GHz is achieved with a 3 dB bandwidth of 11 GHz from 80 to 91 GHz. A good agreement between the simulated and measured results verifies the accuracy of the design procedure. In addition, a multi-stage wide-band BPDA has been designed to show the ability of the proposed topology for design of wide band mmW amplifiers using the CMOS technology. Simulated gain of 20.5 dB with a considerable 3 dB bandwidth of 38 GHz from 30 to 68 GHz is achieved while the noise figure is less than 6 dB in the whole bandwidth. An amplifier figure of merit is defined in terms of gain, noise figure, chip area, band width and power consumption. The results are compared to those of the state of the art to demonstrate the advantages of the proposed circuit topology and presented design techniques. Finally, a Rotman lens is designed and optimized by choosing a very small Focal Lens Ratio (FL), and a high measured efficiency of greater than 30% is achieved while the lens dimensions are less than 6 mm. The lens is designed and implemented using a low cost Alumina substrate and conventional microstrip lines to ease its integration with the active parts of the system.1 yea

Energy autonomous systems : future trends in devices, technology, and systems

The rapid evolution of electronic devices since the beginning of the nanoelectronics era has brought about exceptional computational power in an ever shrinking system footprint. This has enabled among others the wealth of nomadic battery powered wireless systems (smart phones, mp3 players, GPS, …) that society currently enjoys. Emerging integration technologies enabling even smaller volumes and the associated increased functional density may bring about a new revolution in systems targeting wearable healthcare, wellness, lifestyle and industrial monitoring applications

Architecting a One-to-many Traffic-Aware and Secure Millimeter-Wave Wireless Network-in-Package Interconnect for Multichip Systems

With the aggressive scaling of device geometries, the yield of complex Multi Core Single Chip(MCSC) systems with many cores will decrease due to the higher probability of manufacturing defects especially, in dies with a large area. Disintegration of large System-on-Chips(SoCs) into smaller chips called chiplets has shown to improve the yield and cost of complex systems. Therefore, platform-based computing modules such as embedded systems and micro-servers have already adopted Multi Core Multi Chip (MCMC) architectures overMCSC architectures. Due to the scaling of memory intensive parallel applications in such systems, data is more likely to be shared among various cores residing in different chips resulting in a significant increase in chip-to-chip traffic, especially one-to-many traffic. This one-to-many traffic is originated mainly to maintain cache-coherence between many cores residing in multiple chips. Besides, one-to-many traffics are also exploited by many parallel programming models, system-level synchronization mechanisms, and control signals. How-ever, state-of-the-art Network-on-Chip (NoC)-based wired interconnection architectures do not provide enough support as they handle such one-to-many traffic as multiple unicast trafficusing a multi-hop MCMC communication fabric. As a result, even a small portion of such one-to-many traffic can significantly reduce system performance as traditional NoC-basedinterconnect cannot mask the high latency and energy consumption caused by chip-to-chipwired I/Os. Moreover, with the increase in memory intensive applications and scaling of MCMC systems, traditional NoC-based wired interconnects fail to provide a scalable inter-connection solution required to support the increased cache-coherence and synchronization generated one-to-many traffic in future MCMC-based High-Performance Computing (HPC) nodes. Therefore, these computation and memory intensive MCMC systems need an energy-efficient, low latency, and scalable one-to-many (broadcast/multicast) traffic-aware interconnection infrastructure to ensure high-performance. Research in recent years has shown that Wireless Network-in-Package (WiNiP) architectures with CMOS compatible Millimeter-Wave (mm-wave) transceivers can provide a scalable, low latency, and energy-efficient interconnect solution for on and off-chip communication. In this dissertation, a one-to-many traffic-aware WiNiP interconnection architecture with a starvation-free hybrid Medium Access Control (MAC), an asymmetric topology, and a novel flow control has been proposed. The different components of the proposed architecture are individually one-to-many traffic-aware and as a system, they collaborate with each other to provide required support for one-to-many traffic communication in a MCMC environment. It has been shown that such interconnection architecture can reduce energy consumption and average packet latency by 46.96% and 47.08% respectively for MCMC systems. Despite providing performance enhancements, wireless channel, being an unguided medium, is vulnerable to various security attacks such as jamming induced Denial-of-Service (DoS), eavesdropping, and spoofing. Further, to minimize the time-to-market and design costs, modern SoCs often use Third Party IPs (3PIPs) from untrusted organizations. An adversary either at the foundry or at the 3PIP design house can introduce a malicious circuitry, to jeopardize an SoC. Such malicious circuitry is known as a Hardware Trojan (HT). An HTplanted in the WiNiP from a vulnerable design or manufacturing process can compromise a Wireless Interface (WI) to enable illegitimate transmission through the infected WI resulting in a potential DoS attack for other WIs in the MCMC system. Moreover, HTs can be used for various other malicious purposes, including battery exhaustion, functionality subversion, and information leakage. This information when leaked to a malicious external attackercan reveals important information regarding the application suites running on the system, thereby compromising the user profile. To address persistent jamming-based DoS attack in WiNiP, in this dissertation, a secure WiNiP interconnection architecture for MCMC systems has been proposed that re-uses the one-to-many traffic-aware MAC and existing Design for Testability (DFT) hardware along with Machine Learning (ML) approach. Furthermore, a novel Simulated Annealing (SA)-based routing obfuscation mechanism was also proposed toprotect against an HT-assisted novel traffic analysis attack. Simulation results show that,the ML classifiers can achieve an accuracy of 99.87% for DoS attack detection while SA-basedrouting obfuscation could reduce application detection accuracy to only 15% for HT-assistedtraffic analysis attack and hence, secure the WiNiP fabric from age-old and emerging attacks

Exploration and Design of High Performance Variation Tolerant On-Chip Interconnects

Siirretty Doriast

Réalisation, caractérisation et modélisation de nanofils pour application RF

Les composants nano électroniques ont fait l'objet d'intérêt marqué, au sein de la communauté des concepteurs de circuits radiofréquence au cours de ces dernières années. Non seulement ils peuvent présenter des caractéristiques intéressantes, mais ils offrent la perspective d'améliorations de la miniaturisation des composants les plus avancés. Les nanotubes de carbone et les nanofils conducteurs sont attendus comme pouvant potentiellement constituer des blocs utilisables dans les futurs circuits aux très faibles dimensions. Les conducteurs métalliques sont utilisés depuis longtemps pour réaliser des composants passifs dans les circuits intégrés radio fréquence, cependant très peu de travaux ont été menés sur des conducteurs ayant des dimensions nanométriques et fonctionnant dans le domaine millimétrique. L'objectif de cette thèse est d'exploré les propriétés RF de conducteurs métalliques aux dimensions nanométriques et la possibilité de les intégrés dans des circuits utilisant des technologies CMOS. Dans cette thèse, des lignes de transmission et des antennes intégrées sur puce, utilisant des nanofils conducteurs, ont été conçues et réalisées en utilisant un processus de fabrication "top-down". Les caractéristiques en terme de transmission de signal ont été observées expérimentalement dans le domaine millimétrique par la mesure de paramètres S. Deux types de lignes ont été conçus : des lignes micro-ruban de faible épaisseur et des lignes coplanaires. Les caractéristiques en fonction de la fréquence du signal d'excitation ont été analysées. Différents paramètres comme la largeur, l'épaisseur, le nombre de nanofils et la distance entre les nanofils ont été étudiés. De plus, un modèle de propagation basée sur des ondes quasi-TEM a été proposé pour obtenir une compréhension fine du comportement physique des nanofils. Par ailleurs, une étude approfondies concernant les techniques d'épluchage (de-embedding) a été menée afin d'améliorer la précision des mesures. En parallèle, des antennes dipôle et IFA, utilisant des nanofils, ont été réalisées pour tester la transmission sans ligne de propagation. Différentes dimensions de conducteurs et différents types de substrats ont été utilisés pour étudier leurs propriétés et obtenir les meilleures performances.Nano-electronic devices have attracted much attention for the radio frequency engineering community in recent years. They not only exhibit compelling characteristics but show promises to enhance the miniaturization of modern devices. Carbon nanotubes and conducting nanowires are believed to be potential building blocks for ultra-small chip of the future. Metallic wires have long been utilized as the passive components in the RF integrated circuit but there are very few studies on their nanoscale counterpart particularly up to millimeter-wave frequencies. The focus of this thesis is to explore RF properties of metallic nanowires and their potentials to be integrated in CMOS communication technology. In this thesis, transmission lines and on-chip antennas integrated with metallic nanowires were developed enabled by top-down fabrication processes. The signal transmission properties of such devices were characterized well into the mm-wave regime based on two-port S-parameters measurement. Two types of nano-transmission lines were designed: thin film microstrip lines and coplanar waveguides. Their transmission characteristics as a function of frequencies were analysed. Different parameters like the linewidth, thickness, number of nanowires, and the distance between the wires were examined. In addition, a quasi-TEM propagation model was proposed to provide a further insight into the physical behaviours of the nanowires. Moreover, a comprehensive study regarding the de-embedding techniques was carried out in order to improve measurement accuracy. Meanwhile, on-chip dipoles and planar meander-line inverted F antenna were implemented to test the wireless signal transmission of the metallic nanowires. Various wires dimensions and substrates were designed to exploit their characteristics thus facilitating better transmission.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Thermal-Aware Networked Many-Core Systems

Advancements in IC processing technology has led to the innovation and growth happening in the consumer electronics sector and the evolution of the IT infrastructure supporting this exponential growth. One of the most difficult obstacles to this growth is the removal of large amount of heatgenerated by the processing and communicating nodes on the system. The scaling down of technology and the increase in power density is posing a direct and consequential effect on the rise in temperature. This has resulted in the increase in cooling budgets, and affects both the life-time reliability and performance of the system. Hence, reducing on-chip temperatures has become a major design concern for modern microprocessors. This dissertation addresses the thermal challenges at different levels for both 2D planer and 3D stacked systems. It proposes a self-timed thermal monitoring strategy based on the liberal use of on-chip thermal sensors. This makes use of noise variation tolerant and leakage current based thermal sensing for monitoring purposes. In order to study thermal management issues from early design stages, accurate thermal modeling and analysis at design time is essential. In this regard, spatial temperature profile of the global Cu nanowire for on-chip interconnects has been analyzed. It presents a 3D thermal model of a multicore system in order to investigate the effects of hotspots and the placement of silicon die layers, on the thermal performance of a modern ip-chip package. For a 3D stacked system, the primary design goal is to maximise the performance within the given power and thermal envelopes. Hence, a thermally efficient routing strategy for 3D NoC-Bus hybrid architectures has been proposed to mitigate on-chip temperatures by herding most of the switching activity to the die which is closer to heat sink. Finally, an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems has been presented. Various thermal models have been developed and thermal control metrics have been extracted. An efficient thermal-aware application mapping algorithm for a 2D NoC has been presented. It has been shown that the proposed mapping algorithm reduces the effective area reeling under high temperatures when compared to the state of the art.Siirretty Doriast

Design of Wireless Power Transfer and Data Telemetry System for Biomedical Applications

With the advancement of biomedical instrumentation technologies sensor based remote healthcare monitoring system is gaining more attention day by day. In this system wearable and implantable sensors are placed outside or inside of the human body. Certain sensors are needed to be placed inside the human body to acquire the information on the vital physiological phenomena such as glucose, lactate, pH, oxygen, etc. These implantable sensors have associated circuits for sensor signal processing and data transmission. Powering the circuit is always a crucial design issue. Batteries cannot be used in implantable sensors which can come in contact with the blood resulting in serious health risks. An alternate approach is to supply power wirelessly for tether-less and battery- less operation of the circuits.Inductive power transfer is the most common method of wireless power transfer to the implantable sensors. For good inductive coupling, the inductors should have high inductance and high quality factor. But the physical dimensions of the implanted inductors cannot be large due to a number of biomedical constraints. Therefore, there is a need for small sized and high inductance, high quality factor inductors for implantable sensor applications. In this work, design of a multi-spiral solenoidal printed circuit board (PCB) inductor for biomedical application is presented. The targeted frequency for power transfer is 13.56 MHz which is within the license-free industrial, scientific and medical (ISM) band. A figure of merit based optimization technique has been utilized to optimize the PCB inductors. Similar principal is applied to design on-chip inductor which could be a potential solution for further miniaturization of the implantable system. For layered human tissue the optimum frequency of power transfer is 1 GHz for smaller coil size. For this reason, design and optimization of multi-spiral solenoidal integrated inductors for 1 GHz frequency is proposed. Finally, it is demonstrated that the proposed inductors exhibit a better overall performance in comparison with the conventional inductors for biomedical applications