Geometric location and power distribution for discrete heat sources on a vertical flat plate with natural convection

textThe current development of consumer electronics, driven by the effort to manufacture smaller products with increased performance, has amplified the chance for inducing higher thermal stresses to these systems. In an effort to devise more effective cooling methods for these systems, many scholars have studied the convective cooling of discrete heating elements. This report discusses a methodology for fabricating and testing a suitable flat plate design with discrete heating elements for both natural and forced convection cooling experiments. There were two plate design attempts: (i) an aluminum plate and (ii) a R3315 hydrostatic-resistance plastic foam plate. For the purpose of conducting experiments for the discrete heating elements, the foam plate design was found to be an appropriate design. After designing a proper foam plate, several experiments were conducted for the natural convection case. The combination of parameters such as the geometric location and power output ratio between heaters that resulted in the maximum thermal conductance were studied.Mechanical Engineerin

Atom chips on direct bonded copper substrates

We present the use of direct bonded copper (DBC) for the straightforward fabrication of high power atom chips. Atom chips using DBC have several benefits: excellent copper/substrate adhesion, high purity, thick (> 100 microns) copper layers, high substrate thermal conductivity, high aspect ratio wires, the potential for rapid (< 8 hr) fabrication, and three dimensional atom chip structures. Two mask options for DBC atom chip fabrication are presented, as well as two methods for etching wire patterns into the copper layer. The wire aspect ratio that optimizes the magnetic field gradient as a function of power dissipation is determined to be 0.84:1 (height:width). The optimal wire thickness as a function of magnetic trapping height is also determined. A test chip, able to support 100 A of current for 2 s without failing, is used to determine the thermal impedance of the DBC. An assembly using two DBC atom chips to provide magnetic confinement is also shown.Comment: 8 pages, 5 figure

Millimetre Wave Power Measurement

There is currently no traceable power sensor for millimetre wave frequencies above 110 GHz. This thesis investigates a novel approach to remove this limitation by combining the placement of a uniquely designed microchip directly in waveguide. The design of the chip is novel in that it does not rely on a supporting structure or an external antenna when placed in the waveguide. The performance of the design was primarily analysed by computer simulation and verified with the measurement of a scale model. The results show that it is feasible to measure high frequency power by placing a chip directly in waveguide. It is predicted that the chip is able to absorb approximately 60% of incident power. Any further efficiency would require modification of the chip substrate. However, this proposed design should allow the standards institutes a reference that will enable the calibration of equipment to beyond 110 GHz

Evaluation of temperature-performance trade-offs in wireless network-on-chip architectures

Continued scaling of device geometries according to Moore\u27s Law is enabling complete end-user systems on a single chip. Massive multicore processors are enablers for many information and communication technology (ICT) innovations spanning various domains, including healthcare, defense, and entertainment. In the design of high-performance massive multicore chips, power and heat are dominant constraints. Temperature hotspots witnessed in multicore systems exacerbate the problem of reliability in deep submicron technologies. Hence, there is a great need to explore holistic power and thermal optimization and management strategies for the massive multicore chips. High power consumption not only raises chip temperature and cooling cost, but also decreases chip reliability and performance. Thus, addressing thermal concerns at different stages of the design and operation is critical to the success of future generation systems. The performance of a multicore chip is also influenced by its overall communication infrastructure, which is predominantly a Network-on-Chip (NoC). The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency, significant power consumption, and temperature hotspots arising out of long, multi-hop wireline links used in data exchange. On-chip wireless networks are envisioned as an enabling technology to design low power and high bandwidth massive multicore architectures. However, optimizing wireless NoCs for best performance does not necessarily guarantee a thermally optimal interconnection architecture. The wireless links being highly efficient attract very high traffic densities which in turn results in temperature hotspots. Therefore, while the wireless links result in better performance and energy-efficiency, they can also cause temperature hotspots and undermine the reliability of the system. Consequently, the location and utilization of the wireless links is an important factor in thermal optimization of high performance wireless Networks-on-Chip. Architectural innovation in conjunction with suitable power and thermal management strategies is the key for designing high performance yet energy-efficient massive multicore chips. This work contributes to exploration of various the design methodologies for establishing wireless NoC architectures that achieve the best trade-offs between temperature, performance and energy-efficiency. It further demonstrates that incorporating Dynamic Thermal Management (DTM) on a multicore chip designed with such temperature and performance optimized Wireless Network-on-Chip architectures improves thermal profile while simultaneously providing lower latency and reduced network energy dissipation compared to its conventional counterparts

A Manufacturer Design Kit for Multi-Chip Power Module Layout Synthesis

The development of Multi-Chip Power Modules (MCPMs) has been a key factor in recent advancements in power electronics technologies. MCPMs achieve higher power density by combining multiple power semiconductor devices into one package. The work detailed in this thesis is part of an ongoing project to develop a computer-aided design software tool known as PowerSynth for MCPM layout synthesis and optimization. This thesis focuses on the definition and design of a Manufacturer Design Kit (MDK) for PowerSynth, which enables the designer to design an MCPM for a manufacturer’s fabrication process. The MDK is comprised of a layer stack and technology library, design rule checking (DRC), and layout versus schematic checking. File formats have been defined for layer stack and design rule input, and import functions have been written and integrated with the existing user interface and data structures to allow PowerSynth to accept these file formats as a form of input. Finally, an exhaustive DRC function has been implemented to allow the designer to verify that a synthesized layout meets all design rules before committing the design to manufacturing. This function was validated by running DRC on an example layout solution using two different sets of design rules

Skybridge: A New Nanoscale 3-D Computing Framework for Future Integrated Circuits

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, continuing the traditional way of scaling to sub-20nm technologies is proving to be very difficult as MOSFETs are reaching their fundamental performance limits [1] and interconnection bottleneck is dominating IC operational power and performance [2]. Migrating to 3-D, as a way to advance scaling, has been elusive due to inherent customization and manufacturing requirements in CMOS architecture that are incompatible with 3-D organization. Partial attempts with die-die [3] and layer-layer [4] stacking have their own limitations [5]. We propose a new 3-D IC fabric technology, Skybridge [6], which offers paradigm shift in technology scaling as well as design. We co-architect Skybridge’s core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D template. Our extensive bottom-up simulations, accounting for detailed material system structures, manufacturing process, device, and circuit parasitics, carried through for several designs including a designed microprocessor, reveal a 30-60x density, 3.5x performance/watt benefits, and 10x reduction in interconnect lengths vs. scaled 16-nm CMOS [6]. Fabric-level heat extraction features are found to be effective in managing IC thermal profiles in 3-D. This 3-D integrated fabric proposal overcomes the current impasse of CMOS in a manner that can be immediately adopted, and offers unique solution to continue technology scaling in the 21st century

Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, scaling to sub-20nm technologies is proving to be challenging as MOSFETs are reaching their fundamental limits and interconnection bottleneck is dominating IC operational power and performance. Migrating to 3-D, as a way to advance scaling, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization. Partial attempts with die-die and layer-layer stacking have their own limitations. We propose a 3-D IC fabric technology, Skybridge[TM], which offers paradigm shift in technology scaling as well as design. We co-architect Skybridge's core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D template. Our extensive bottom-up simulations, accounting for detailed material system structures, manufacturing process, device, and circuit parasitics, carried through for several designs including a designed microprocessor, reveal a 30-60x density, 3.5x performance per watt benefits, and 10X reduction in interconnect lengths vs. scaled 16-nm CMOS. Fabric-level heat extraction features are shown to successfully manage IC thermal profiles in 3-D. Skybridge can provide continuous scaling of integrated circuits beyond CMOS in the 21st century.Comment: 53 Page

Heat rejection sublimator

A sublimator includes a sublimation plate having a thermal element disposed adjacent to a feed water channel and a control point disposed between at least a portion of the thermal element and a large pore substrate. The control point includes a sintered metal material. A method of dissipating heat using a sublimator includes a sublimation plate having a thermal element and a control point. The thermal element is disposed adjacent to a feed water channel and the control point is disposed between at least a portion of the thermal element and a large pore substrate. The method includes controlling a flow rate of feed water to the large pore substrate at the control point and supplying heated coolant to the thermal element. Sublimation occurs in the large pore substrate and the controlling of the flow rate of feed water is independent of time. A sublimator includes a sublimation plate having a thermal element disposed adjacent to a feed water channel and a control point disposed between at least a portion of the thermal element and a large pore substrate. The control point restricts a flow rate of feed water from the feed water channel to the large pore substrate independent of time