Optimal Positions of Twists in Global On-Chip Differential Interconnects

Abstract—Crosstalk limits the achievable data rate of global on-chip interconnects on large CMOS ICs. This is especially the case, if low-swing signaling is used to reduce power consumption. Differential interconnects provide a solution for most crosstalk and noise sources, but not for neighbor-to-neighbor crosstalk in a data bus. This neighbor-to-neighbor crosstalk can be reduced with twists in the differential interconnect-pairs. To reduce via resistance and metal layer use, we use as few twists as possible by placing only one twist in every even interconnect-pair and only two twists in every odd interconnect-pair. Analysis shows that there are optimal positions for the twists, which depend on the termination impedances of the interconnects. Theory and measurements on a 10 mm long bus in 0.13 μm CMOS show that only one twist at 50% of the even interconnect-pairs, two twists at 30% and 70% of the odd interconnect-pairs and both a low-ohmic source and a low-ohmic load impedance are very effective in mitigating the crosstalk

Development of a Solar Array Drive Assembly for CubeSat

Small satellites and in particular CubeSats, have increasingly become more viable as platforms for payloads typically requiring much larger bus structures. As advances in technology make payloads and instruments for space missions smaller, lighter and more power efficient, a niche market is emerging from the university community to perform rapidly developed, low-cost missions on very small spacecraft - micro, nano, and picosatellites. In just the last few years, imaging, biological and new technology demonstration missions have been either proposed or have flown using variations of the CubeSat structure as a basis. As these missions have become more complex, and the CubeSat standard has increased in both size (number of cubes) and mass, available power has become an issue. Body-mounted solar cells provide a minimal amount of power; deployable arrays improve on that baseline but are still limited. To truly achieve maximum power, deployed tracked arrays are necessary. To this end, Honeybee Robotics Spacecraft Mechanisms Corporation, along with MMA of Nederland Colorado, has developed a solar array drive assembly (SADA) and deployable solar arrays specifically for CubeSat missions. In this paper, we discuss the development of the SADA

Efficiently mapping high-performance early vision algorithms onto multicore embedded platforms

The combination of low-cost imaging chips and high-performance, multicore, embedded processors heralds a new era in portable vision systems. Early vision algorithms have the potential for highly data-parallel, integer execution. However, an implementation must operate within the constraints of embedded systems including low clock rate, low-power operation and with limited memory. This dissertation explores new approaches to adapt novel pixel-based vision algorithms for tomorrow's multicore embedded processors. It presents : - An adaptive, multimodal background modeling technique called Multimodal Mean that achieves high accuracy and frame rate performance with limited memory and a slow-clock, energy-efficient, integer processing core. - A new workload partitioning technique to optimize the execution of early vision algorithms on multi-core systems. - A novel data transfer technique called cat-tail dma that provides globally-ordered, non-blocking data transfers on a multicore system. By using efficient data representations, Multimodal Mean provides comparable accuracy to the widely used Mixture of Gaussians (MoG) multimodal method. However, it achieves a 6.2x improvement in performance while using 18% less storage than MoG while executing on a representative embedded platform. When this algorithm is adapted to a multicore execution environment, the new workload partitioning technique demonstrates an improvement in execution times of 25% with only a 125 ms system reaction time. It also reduced the overall number of data transfers by 50%. Finally, the cat-tail buffering technique reduces the data-transfer latency between execution cores and main memory by 32.8% over the baseline technique when executing Multimodal Mean. This technique concurrently performs data transfers with code execution on individual cores, while maintaining global ordering through low-overhead scheduling to prevent collisions.Ph.D.Committee Chair: Wills, Scott; Committee Co-Chair: Wills, Linda; Committee Member: Bader, David; Committee Member: Davis, Jeff; Committee Member: Hamblen, James; Committee Member: Lanterman, Aaro

Naval Remote Ocean Sensing System (NROSS) study

A set of hardware similar to the SEASAT A configuration requirement, suitable for installation and operation aboard a NOAA-D bus and a budgetary cost for one (1) protoflight model was provided. The scatterometer sensor is conceived as one of several sensors for the Navy Remote Ocean Sensing System (NROSS) Satellite Program. Deliverables requested were to include a final report with appropriate sketches and block diagrams showing the scatterometer design/configuration and a budgetary cost for all labor and materials to design, fabricate, test, and integrate this hardware into a NOAA-D satellite bus. This configuration consists of two (2) hardware assembles - a transmitter/receiver (T/R) assembly and an integrated electronics assembly (IEA). The T/R assembly as conceived is best located at the extreme opposite end of the satellite away from the solar array assembly and oriented in position to enable one surface of the assembly to have unobstructed exposure to space. The IEA is planned to be located at the bottom (Earth viewing) side of the satellite and requires a radiating plate

Space station data system analysis/architecture study. Task 2: Options development DR-5. Volume 1: Technology options

The second task in the Space Station Data System (SSDS) Analysis/Architecture Study is the development of an information base that will support the conduct of trade studies and provide sufficient data to make key design/programmatic decisions. This volume identifies the preferred options in the technology category and characterizes these options with respect to performance attributes, constraints, cost, and risk. The technology category includes advanced materials, processes, and techniques that can be used to enhance the implementation of SSDS design structures. The specific areas discussed are mass storage, including space and round on-line storage and off-line storage; man/machine interface; data processing hardware, including flight computers and advanced/fault tolerant computer architectures; and software, including data compression algorithms, on-board high level languages, and software tools. Also discussed are artificial intelligence applications and hard-wire communications

Aeronautical Engineering: A continuing bibliography, supplement 124

This bibliography, lists 450 reports, articles, and other documents introduced into the NASA scientific and technical information system in June 1980

High-level services for networks-on-chip

Future technology trends envision that next-generation Multiprocessors Systems-on- Chip (MPSoCs) will be composed of a combination of a large number of processing and storage elements interconnected by complex communication architectures. Communication and interconnection between these basic blocks play a role of crucial importance when the number of these elements increases. Enabling reliable communication channels between cores becomes therefore a challenge for system designers. Networks-on-Chip (NoCs) appeared as a strategy for connecting and managing the communication between several design elements and IP blocks, as required in complex Systems-on-Chip (SoCs). The topic can be considered as a multidisciplinary synthesis of multiprocessing, parallel computing, networking, and on- chip communication domains. Networks-on-Chip, in addition to standard communication services, can be employed for providing support for the implementation of system-level services. This dissertation will demonstrate how high-level services can be added to an MPSoC platform by embedding appropriate hardware/software support in the network interfaces (NIs) of the NoC. In this dissertation, the implementation of innovative modules acting in parallel with protocol translation and data transmission in NIs is proposed and evaluated. The modules can support the execution of the high-level services in the NoC at a relatively low cost in terms of area and energy consumption. Three types of services will be addressed and discussed: security, monitoring, and fault tolerance. With respect to the security aspect, this dissertation will discuss the implementation of an innovative data protection mechanism for detecting and preventing illegal accesses to protected memory blocks and/or memory mapped peripherals. The second aspect will be addressed by proposing the implementation of a monitoring system based on programmable multipurpose monitoring probes aimed at detecting NoC internal events and run-time characteristics. As last topic, new architectural solutions for the design of fault tolerant network interfaces will be presented and discussed

Marshall Space Flight Center Electromagnetic Compatibility Design and Interference Control (MEDIC) handbook

The purpose of the MEDIC Handbook is to provide practical and helpful information in the design of electrical equipment for electromagnetic compatibility (EMS). Included is the definition of electromagnetic interference (EMI) terms and units as well as an explanation of the basic EMI interactions. An overview of typical NASA EMI test requirements and associated test setups is given. General design techniques to minimize the risk of EMI and EMI suppression techniques at the board and equipment interface levels are presented. The Handbook contains specific EMI test compliance design techniques and retrofit fixes for noncompliant equipment. Also presented are special tests that are useful in the design process or in instances of specification noncompliance

Topological and subsystem codes on low-degree graphs with flag qubits

In this work we introduce two code families, which we call the heavy hexagon code and heavy square code. Both code families are implemented by assigning physical data and ancilla qubits to both vertices and edges of low degree graphs. Such a layout is particularly suitable for superconducting qubit architectures to minimize frequency collisions and crosstalk. In some cases, frequency collisions can be reduced by several orders of magnitude. The heavy hexagon code is a hybrid surface/Bacon-Shor code mapped onto a (heavy) hexagonal lattice whereas the heavy square code is the surface code mapped onto a (heavy) square lattice. In both cases, the lattice includes all the ancilla qubits required for fault-tolerant error-correction. Naively, the limited qubit connectivity might be thought to limit the error-correcting capability of the code to less than its full distance. Therefore, essential to our construction is the use of flag qubits. We modify minimum weight perfect matching decoding to efficiently and scalably incorporate information from measurements of the flag qubits and correct up to the full code distance while respecting the limited connectivity. Simulations show that high threshold values for both codes can be obtained using our decoding protocol. Further, our decoding scheme can be adapted to other topological code families.Comment: 20 pages, 21 figures, Comments welcome! V2 conforms to journal specification