An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing

In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with `memimpedace' elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at 100 degree Celsius across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance's quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses).Comment: This work has been accepted to the IEEE TCAS-

Designing Novel Hardware Security Primitives for Smart Computing Devices

Smart computing devices are miniaturized electronics devices that can sense their surroundings, communicate, and share information autonomously with other devices to work cohesively. Smart devices have played a major role in improving quality of the life and boosting the global economy. They are ubiquitously present, smart home, smart city, smart girds, industry, healthcare, controlling the hazardous environment, and military, etc. However, we have witnessed an exponential rise in potential threat vectors and physical attacks in recent years. The conventional software-based security approaches are not suitable in the smart computing device, therefore, hardware-enabled security solutions have emerged as an attractive choice. Developing hardware security primitives, such as True Random Number Generator (TRNG) and Physically Unclonable Function (PUF) from electrical properties of the sensor could be a novel research direction. Secondly, the Lightweight Cryptographic (LWC) ciphers used in smart computing devices are found vulnerable against Correlation Power Analysis (CPA) attack. The CPA performs statistical analysis of the power consumption of the cryptographic core and reveals the encryption key. The countermeasure against CPA results in an increase in energy consumption, therefore, they are not suitable for battery operated smart computing devices. The primary goal of this dissertation is to develop novel hardware security primitives from existing sensors and energy-efficient LWC circuit implementation with CPA resilience. To achieve these. we focus on developing TRNG and PUF from existing photoresistor and photovoltaic solar cell sensors in smart devices Further, we explored energy recovery computing (also known as adiabatic computing) circuit design technique that reduces the energy consumption compared to baseline CMOS logic design and same time increasing CPA resilience in low-frequency applications, e.g. wearable fitness gadgets, hearing aid and biomedical instruments. The first contribution of this dissertation is to develop a TRNG prototype from the uncertainty present in photoresistor sensors. The existing sensor-based TRNGs suffer a low random bit generation rate, therefore, are not suitable in real-time applications. The proposed prototype has an average random bit generation rate of 8 kbps, 32 times higher than the existing sensor-based TRNG. The proposed lightweight scrambling method results in random bit entropy close to ideal value 1. The proposed TRNG prototype passes all 15 statistical tests of the National Institute of Standards and Technology (NIST) Statistical Test Suite with quality performance. The second contribution of this dissertation is to develop an integrated TRNG-PUF designed using photovoltaic solar cell sensors. The TRNG and PUF are mutually independent in the way they are designed, therefore, integrating them as one architecture can be beneficial in resource-constrained computing devices. We propose a novel histogram-based technique to segregate photovoltaic solar cell sensor response suitable for TRNG and PUF respectively. The proposed prototype archives approximately 34\% improvement in TRNG output. The proposed prototype achieves an average of 92.13\% reliability and 50.91\% uniformity performance in PUF response. The proposed sensor-based hardware security primitives do not require additional interfacing hardware. Therefore, they can be ported as a software update on existing photoresistor and photovoltaic sensor-based devices. Furthermore, the sensor-based design approach can identify physically tempered and faulty sensor nodes during authentication as their response bit differs. The third contribution is towards the development of a novel 2-phase sinusoidal clocking implementation, 2-SPGAL for existing Symmetric Pass Gate Adiabatic Logic (SPGAL). The proposed 2-SPGAL logic-based LWC cipher PRESENT shows an average of 49.34\% energy saving compared to baseline CMOS logic implementation. Furthermore, the 2-SPGAL prototype has an average of 22.76\% better energy saving compared to 2-EE-SPFAL (2-phase Energy-Efficient-Secure Positive Feedback Adiabatic Logic). The proposed 2-SPGAL was tested for energy-efficiency performance for the frequency range of 50 kHz to 250 kHz, used in healthcare gadgets and biomedical instruments. The proposed 2-SPGAL based design saves 16.78\% transistor count compared to 2-EE-SPFAL counterpart. The final contribution is to explore Clocked CMOS Adiabatic Logic (CCAL) to design a cryptographic circuit. Previously proposed 2-SPGAL and 2-EE-SPFAL uses two complementary pairs of the transistor evaluation network, thus resulting in a higher transistor count compared to the CMOS counterpart. The CCAL structure is very similar to CMOS and unlike 2-SPGAL and 2-EE-SPFAL, it does not require discharge circuitry to improve security performance. The case-study implementation LWC cipher PRESENT S-Box using CCAL results into 45.74\% and 34.88\% transistor count saving compared to 2-EE-SPFAL and 2-SPGAL counterpart. Furthermore, the case-study implementation using CCAL shows more than 95\% energy saving compared to CMOS logic at frequency range 50 kHz to 125 kHz, and approximately 60\% energy saving at frequency 250 kHz. The case study also shows 32.67\% and 11.21\% more energy saving compared to 2-EE-SPFAL and 2-SPGAL respectively at frequency 250 kHz. We also show that 200 fF of tank capacitor in the clock generator circuit results in optimum energy and security performance in CCAL

Apollo docking test device design study final report

Docking simulation system for confirming Apollo probe design and drogue docking mechanisms under simulated space condition

Antenna-coupled silicon-organic hybrid integrated photonic crystal modulator for broadband electromagnetic wave detection

In this work, we design, fabricate and characterize a compact, broadband and highly sensitive integrated photonic electromagnetic field sensor based on a silicon-organic hybrid modulator driven by a bowtie antenna. The large electro-optic (EO) coefficient of organic polymer, the slow-light effects in the silicon slot photonic crystal waveguide (PCW), and the broadband field enhancement provided by the bowtie antenna, are all combined to enhance the interaction of microwaves and optical waves, enabling a high EO modulation efficiency and thus a high sensitivity. The modulator is experimentally demonstrated with a record-high effective in-device EO modulation efficiency of r33=1230pm/V. Modulation response up to 40GHz is measured, with a 3-dB bandwidth of 11GHz. The slot PCW has an interaction length of 300um, and the bowtie antenna has an area smaller than 1cm2. The bowtie antenna in the device is experimentally demonstrated to have a broadband characteristics with a central resonance frequency of 10GHz, as well as a large beam width which enables the detection of electromagnetic waves from a large range of incident angles. The sensor is experimentally demonstrated with a minimum detectable electromagnetic power density of 8.4mW/m2 at 8.4GHz, corresponding to a minimum detectable electric field of 2.5V/m and an ultra-high sensitivity of 0.000027V/m Hz^-1/2 ever demonstrated. To the best of our knowledge, this is the first silicon-organic hybrid device and also the first PCW device used for the photonic detection of electromagnetic waves. Finally, we propose some future work, including a Teraherz wave sensor based on antenna-coupled electro-optic polymer filled plasmonic slot waveguide, as well as a fully packaged and tailgated device.Comment: 20 pages, 16 figure

Cryogenic Control Beyond 100 Qubits

Quantum computation has been a major focus of research in the past two decades, with recent experiments demonstrating basic algorithms on small numbers of qubits. A large-scale universal quantum computer would have a profound impact on science and technology, providing a solution to several problems intractable for classical computers. To realise such a machine, today's small experiments must be scaled up, and a system must be built which provides control and measurement of many hundreds of qubits. A device of this scale is challenging: qubits are highly sensitive to their environment, and sophisticated isolation techniques are required to preserve the qubits' fragile states. Solid-state qubits require deep-cryogenic cooling to suppress thermal excitations. Yet current state-of-the-art experiments use room-temperature electronics which are electrically connected to the qubits. This thesis investigates various scalable technologies and techniques which can be used to control quantum systems. With the requirements for semiconductor spin-qubits in mind, several custom electronic systems, to provide quantum control from deep cryogenic temperatures, are designed and measured. A system architecture is proposed for quantum control, providing a scalable approach to executing quantum algorithms on a large number of qubits. Control of a gallium arsenide qubit is demonstrated using a cryogenically operated FPGA driving custom gallium arsenide switches. The cryogenic performance of a commercial FPGA is measured, as the main logic processor in a cryogenic quantum control system, and digital-to-analog converters are analysed during cryogenic operation. Recent work towards a 100-qubit cryogenic control system is shown, including the design of interconnect solutions and multiplexing circuitry. With qubit fidelity over the fault-tolerant threshold for certain error correcting codes, accompanying control platforms will play a key role in the development of a scalable quantum machine

Silicon - polymer hybrid integrated microwave photonic devices for optical interconnects and electromagnetic wave detection

textThe accelerating increase in information traffic demands the expansion of optical access network systems that require high-performance optical and photonic components. In short-range communication links, optical interconnects have been widely accepted as a viable approach to solve the problems that copper based electrical interconnects have encountered in keeping up with the surge in the data rate demand over the last decades. Low cost, ease of fabrication, and integration capabilities of low optical-loss polymers make them attractive for integrated photonic applications to support futuristic data communication networks. In addition to passive wave-guiding components, electro-optic (EO) polymers consisting of a polymeric matrix doped with organic nonlinear chromophores have enabled wide-RF-bandwidth and low-power active photonic devices. Beside board level passive and active optical components, on-chip micro- or nano-photonic devices have been made possible by the hybrid integration of EO polymers onto the silicon platform. In recent years, silicon photonics have attracted a significant amount of attentions, because it offers compact device size and the potential of complementary metal–oxide–semiconductor (CMOS) compatible photonic integrated circuits. The combination of silicon photonics and EO polymers can enable miniaturized and high-performance hybrid integrated photonic devices, such as electro-optic modulators, optical interconnects, and microwave photonic sensors. Silicon photonic crystal waveguides (PCWs) exhibit slow-light effects which are beneficial for device miniaturization. Especially, EO polymer filled silicon slotted PCWs further reduce the device size and enhance the device performance by combining the best of these two systems. The potential applications of these silicon-polymer hybrid integrated devices include not only optical interconnects, but also optical sensing and microwave photonics. In this dissertation, the design, fabrication, and characterization of several types of silicon-polymer hybrid photonic devices will be presented, including EO polymer filled silicon PCW modulators for on-chip optical interconnects, antenna-coupled optical modulators for electromagnetic wave detections, and low-loss strip-to-slot PCW mode converters. In addition, some polymer-based devices and silicon-based photonic devices will also be presented, such as traveling wave electro-optic polymer modulators based on domain-inversion directional couplers, and silicon thermo-optic switches based on coupled photonic crystal microcavities. Furthermore, some microwave (or RF) components such as integrated broadband bowtie antennas for microwave photonic applications will be covered. Some on-going work or suggested future work will also be introduced, including in-device pyroelectric poling for EO polymer filled silicon slot PCWs, millimeter- or Terahertz-wave sensors based on EO polymer filled plasmonic slot waveguide, low-loss silicon-polymer hybrid slot photonic crystal waveguides fabricated by CMOS foundry, logic devices based on EO polymer microring resonators, and so on.Electrical and Computer Engineerin

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor