Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes

Bidirectional neural interfaces are tools designed to “communicate” with the brain via recording and modulation of neuronal activity. The bidirectional interface systems have been adopted for many applications. Neuroscientists employ them to map neuronal circuits through precise stimulation and recording. Medical doctors deploy them as adaptable medical devices which control therapeutic stimulation parameters based on monitoring real-time neural activity. Brain-machine-interface (BMI) researchers use neural interfaces to bypass the nervous system and directly control neuroprosthetics or brain-computer-interface (BCI) spellers. In bidirectional interfaces, the implantable transducers as well as the corresponding electronic circuits and systems face several challenges. A high channel count, low power consumption, and reduced system size are desirable for potential chronic deployment and wider applicability. Moreover, a neural interface designed for robust closed-loop operation requires the mitigation of stimulation artifacts which corrupt the recorded signals. This dissertation introduces several techniques targeting low power consumption, small size, and reduction of stimulation artifacts. These techniques are implemented for extracellular electrophysiological recording and two stimulation modalities: direct current stimulation for closed-loop control of seizure detection/quench and optical stimulation for optogenetic studies. While the two modalities differ in their mechanisms, hardware implementation, and applications, they share many crucial system-level challenges. The first method aims at solving the critical issue of stimulation artifacts saturating the preamplifier in the recording front-end. To prevent saturation, a novel mixed-signal stimulation artifact cancellation circuit is devised to subtract the artifact before amplification and maintain the standard input range of a power-hungry preamplifier. Additional novel techniques have been also implemented to lower the noise and power consumption. A common average referencing (CAR) front-end circuit eliminates the cross-channel common mode noise by averaging and subtracting it in analog domain. A range-adapting SAR ADC saves additional power by eliminating unnecessary conversion cycles when the input signal is small. Measurements of an integrated circuit (IC) prototype demonstrate the attenuation of stimulation artifacts by up to 42 dB and cross-channel noise suppression by up to 39.8 dB. The power consumption per channel is maintained at 330 nW, while the area per channel is only 0.17 mm2. The second system implements a compact headstage for closed-loop optogenetic stimulation and electrophysiological recording. This design targets a miniaturized form factor, high channel count, and high-precision stimulation control suitable for rodent in-vivo optogenetic studies. Monolithically integrated optoelectrodes (which include 12 µLEDs for optical stimulation and 12 electrical recording sites) are combined with an off-the-shelf recording IC and a custom-designed high-precision LED driver. 32 recording and 12 stimulation channels can be individually accessed and controlled on a small headstage with dimensions of 2.16 x 2.38 x 0.35 cm and mass of 1.9 g. A third system prototype improves the optogenetic headstage prototype by furthering system integration and improving power efficiency facilitating wireless operation. The custom application-specific integrated circuit (ASIC) combines recording and stimulation channels with a power management unit, allowing the system to be powered by an ultra-light Li-ion battery. Additionally, the µLED drivers include a high-resolution arbitrary waveform generation mode for shaping of µLED current pulses to preemptively reduce artifacts. A prototype IC occupies 7.66 mm2, consumes 3.04 mW under typical operating conditions, and the optical pulse shaping scheme can attenuate stimulation artifacts by up to 3x with a Gaussian-rise pulse rise time under 1 ms.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147674/1/mendrela_1.pd

Facilitated event-related power modulations during transcranial alternating current stimulation (tACS) revealed by concurrent tACS-MEG

Non-invasive approaches to modulate oscillatory activity in the brain are increasingly popular in the scientific community. Transcranial alternating current stimulation (tACS) has been shown to modulate neural oscillations in a frequency-specific manner. However, due to a massive stimulation artifact at the targeted frequency, little is known about effects of tACS during stimulation. It remains unclear how the continuous application of tACS affects event-related oscillations during cognitive tasks. Depending on whether tACS influences pre- or post-stimulus oscillations, or both, the endogenous, event-related oscillatory dynamics could be pushed in various directions or not at all. A better understanding of these effects is crucial to plan, predict, and understand outcomes of solely behavioral tACS experiments. In the present study, a recently proposed procedure to suppress tACS artifacts by projecting MEG data into source-space using spatial filtering was utilized to recover event-related power modulations in the alpha-band during a mental rotation task. MEG data of 25 human subjects was continuously recorded. After 10-minute baseline measurement, participants received either 20 minutes of tACS at their individual alpha frequency or sham stimulation. Another 40 minutes of MEG data were acquired thereafter. Data were projected into source-space and carefully examined for residual artifacts. Results revealed strong facilitation of event-related power modulations in the alpha-band during tACS application. These results provide first direct evidence that tACS does not counteract top-down suppression of intrinsic oscillations, but rather enhances pre-existent power modulations within the range of the individual alpha (= stimulation) frequency

Event related (de-)synchronization patterns in actual and imagined hand movements

Projecte final de carrera realitzat en col.laboració amb Philips ResearchThis project presents different signal processing techniques, such as Principal Component Analysis (PCA) and Common Spatial Patterns (CSP), applied to characterize the reactivity of central rhythms in the alpha and beta bands during self paced voluntary and imaginary movement. The idea is to allow people to control devices, or interact with machines by simply thinking. To do so, we monitor the brain activity using electroencephalogram (EEG) measurements which record the signals from electrodes positioned on the scalp. The objective is to use motor imagery signals to build a brain computer interface, able to learn from data analyzed before, using the properties of neural networks. The possibility of designing an intuitive communication system between a brain and a computer, available to be operated by everyone, even by people with severe motor impairments, is the main objective of this stud

A Novel Power-Efficient Wireless Multi-channel Recording System for the Telemonitoring of Electroencephalography (EEG)

This research introduces the development of a novel EEG recording system that is modular, batteryless, and wireless (untethered) with the supporting theoretical foundation in wireless communications and related design elements and circuitry. Its modular construct overcomes the EEG scaling problem and makes it easier for reconfiguring the hardware design in terms of the number and placement of electrodes and type of standard EEG system contemplated for use. In this development, portability, lightweight, and applicability to other clinical applications that rely on EEG data are sought. Due to printer tolerance, the 3D printed cap consists of 61 electrode placements. This recording capacity can however extend from 21 (as in the international 10-20 systems) up to 61 EEG channels at sample rates ranging from 250 to 1000 Hz and the transfer of the raw EEG signal using a standard allocated frequency as a data carrier. The main objectives of this dissertation are to (1) eliminate the need for heavy mounted batteries, (2) overcome the requirement for bulky power systems, and (3) avoid the use of data cables to untether the EEG system from the subject for a more practical and less restrictive setting. Unpredictability and temporal variations of the EEG input make developing a battery-free and cable-free EEG reading device challenging. Professional high-quality and high-resolution analog front ends are required to capture non-stationary EEG signals at microvolt levels. The primary components of the proposed setup are the wireless power transmission unit, which consists of a power amplifier, highly efficient resonant-inductive link, rectification, regulation, and power management units, as well as the analog front end, which consists of an analog to digital converter, pre-amplification unit, filtering unit, host microprocessor, and the wireless communication unit. These must all be compatible with the rest of the system and must use the least amount of power possible while minimizing the presence of noise and the attenuation of the recorded signal A highly efficient resonant-inductive coupling link is developed to decrease power transmission dissipation. Magnetized materials were utilized to steer electromagnetic flux and decrease route and medium loss while transmitting the required energy with low dissipation. Signal pre-amplification is handled by the front-end active electrodes. Standard bio-amplifier design approaches are combined to accomplish this purpose, and a thorough investigation of the optimum ADC, microcontroller, and transceiver units has been carried out. We can minimize overall system weight and power consumption by employing battery-less and cable-free EEG readout system designs, consequently giving patients more comfort and freedom of movement. Similarly, the solutions are designed to match the performance of medical-grade equipment. The captured electrical impulses using the proposed setup can be stored for various uses, including classification, prediction, 3D source localization, and for monitoring and diagnosing different brain disorders. All the proposed designs and supporting mathematical derivations were validated through empirical and software-simulated experiments. Many of the proposed designs, including the 3D head cap, the wireless power transmission unit, and the pre-amplification unit, are already fabricated, and the schematic circuits and simulation results were based on Spice, Altium, and high-frequency structure simulator (HFSS) software. The fully integrated head cap to be fabricated would require embedding the active electrodes into the 3D headset and applying current technological advances to miniaturize some of the design elements developed in this dissertation

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Tracking Control for Non-Minimum Phase System and Brain Computer Interface

For generations, humans dreamed about the ability to communicate and interact with machines through thought alone or to create devices that can peer into a person’s mind and thoughts. Researchers have developed new technologies to create brain computer interfaces (BCIs), communication systems that do not depend on the brain’s normal output pathways of peripheral nerves and muscles. The objective of the first part of this thesis is to develop a new BCI based on electroencephalography (EEG) to move a computer cursor over a short training period in real time. The work motivations of this part are to increase: speed and accuracy, as in BCI settings, subject has a few seconds to make a selection with a relatively high accuracy. Recently, improvements have been developed to make EEG more accurate by increasing the spatial resolution. One such improvement is the application of the surface Laplacian to the EEG, the second spatial derivative. Tripolar concentric ring electrodes (TCREs) automatically perform the Laplacian on the surface potentials and provide better spatial selectivity and signal-to-noise ratio than conventional EEG that is recorded with conventional disc electrodes. Another important feature using TCRE is the capability to record the EEG and the TCRE EEG (tEEG) signals concurrently from the same location on the scalp for the same electrical activity coming from the brain. In this part we also demonstrate that tEEG signals can enable users to control a computer cursor rapidly in different directions with significantly higher accuracy during their first session of training for 1D and 2D cursor control. Output tracking control of non-minimum phase systems is a highly challenging problem encountered in many practical engineering applications. Classical inversion techniques provide exact output tracking but lead to internal instability, whereas modern inversion methods provide stable asymptotic tracking but produce large transient errors. Both methods provide an approximation of feedback control, which leads to non robust systems, very sensitive to noise, considerable tracking errors and a significant singularity problem. Aiming at the problem of system inversion to the true system, the objective of the second part of this thesis is to develop a new method based on true inversion for minimum phase system and approximate inversion for non-minimum phase systems. The proposed algorithm is automatic and has minimal computational complexities which make it suitable for real-time control. The process to develop the proposed algorithm is partitioned into (1) minimum phase feedforward inverse filter, and (2) non-minimum phase inversion. In a minimum phase inversion, we consider the design of a feedforward controller to invert the response of a feedback loop that has stable zero locations. The complete control system consists of a feedforward controller cascaded with a closed-loop system. The outputs of the resulting inverse filter are delayed versions of the corresponding reference input signals, and delays are given by the vector relative degree of the closed-loop

A HIGHLY-SCALABLE DC-COUPLED DIRECT-ADC NEURAL RECORDING CHANNEL ARCHITECTURE WITH INPUT-ADAPTIVE RESOLUTION

This thesis presents the design, development, and characterization of a novel neural recording channel architecture with (a) quantization resolution that is adaptive to the input signal's level of activity, (b) fully-dynamic power consumption that is linearly proportional to the recording resolution, and (c) immunity to DC offset and drifts at the input. Our results demonstrate the proposed design's capability in conducting neural recording with near lossless input-adaptive data compression, leading to a significant reduction in the energy required for both recording and data transmission, hence allowing for a potential high scaling of the number of recording channels integrated on a single implanted microchip without the need to increase the power budget. The proposed channel with the implemented compression technique is implemented in a standard 130nm CMOS technology with overall power consumption of 7.6uW and active area of 92×92µm for the implemented digital-backend

A HIGHLY-SCALABLE DC-COUPLED DIRECT-ADC NEURAL RECORDING CHANNEL ARCHITECTURE WITH INPUT-ADAPTIVE RESOLUTION

This thesis presents the design, development, and characterization of a novel neural recording channel architecture with (a) quantization resolution that is adaptive to the input signal's level of activity, (b) fully-dynamic power consumption that is linearly proportional to the recording resolution, and (c) immunity to DC offset and drifts at the input. Our results demonstrate the proposed design's capability in conducting neural recording with near lossless input-adaptive data compression, leading to a significant reduction in the energy required for both recording and data transmission, hence allowing for a potential high scaling of the number of recording channels integrated on a single implanted microchip without the need to increase the power budget. The proposed channel with the implemented compression technique is implemented in a standard 130nm CMOS technology with overall power consumption of 7.6uW and active area of 9292m for the implemented digital-backend

Event related (de-)synchronization patterns in actual and imagined hand movements

Projecte final de carrera realitzat en col.laboració amb Philips ResearchThis project presents different signal processing techniques, such as Principal Component Analysis (PCA) and Common Spatial Patterns (CSP), applied to characterize the reactivity of central rhythms in the alpha and beta bands during self paced voluntary and imaginary movement. The idea is to allow people to control devices, or interact with machines by simply thinking. To do so, we monitor the brain activity using electroencephalogram (EEG) measurements which record the signals from electrodes positioned on the scalp. The objective is to use motor imagery signals to build a brain computer interface, able to learn from data analyzed before, using the properties of neural networks. The possibility of designing an intuitive communication system between a brain and a computer, available to be operated by everyone, even by people with severe motor impairments, is the main objective of this stud

Low Power Circuits for Smart Flexible ECG Sensors

Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor provides an affordable, convenient and comfortable in-home monitoring solution. The three critical building blocks of the ECG sensor i.e., analog frontend (AFE), QRS detector, and cardiac arrhythmia classifier (CAC), are studied in this research. A fully differential difference amplifier (FDDA) based AFE that employs DC-coupled input stage increases the input impedance and improves CMRR. A parasitic capacitor reuse technique is proposed to improve the noise/area efficiency and CMRR. An on-body DC bias scheme is introduced to deal with the input DC offset. Implemented in 0.35m CMOS process with an area of 0.405mm2, the proposed AFE consumes 0.9W at 1.8V and shows excellent noise effective factor of 2.55, and CMRR of 76dB. Experiment shows the proposed AFE not only picks up clean ECG signal with electrodes placed as close as 2cm under both resting and walking conditions, but also obtains the distinct -wave after eye blink from EEG recording. A personalized QRS detection algorithm is proposed to achieve an average positive prediction rate of 99.39% and sensitivity rate of 99.21%. The user-specific template avoids the complicate models and parameters used in existing algorithms while covers most situations for practical applications. The detection is based on the comparison of the correlation coefficient of the user-specific template with the ECG segment under detection. The proposed one-target clustering reduced the required loops. A continuous-in-time discrete-in-amplitude (CTDA) artificial neural network (ANN) based CAC is proposed for the smart ECG sensor. The proposed CAC achieves over 98% classification accuracy for 4 types of beats defined by AAMI (Association for the Advancement of Medical Instrumentation). The CTDA scheme significantly reduces the input sample numbers and simplifies the sample representation to one bit. Thus, the number of arithmetic operations and the ANN structure are greatly simplified. The proposed CAC is verified by FPGA and implemented in 0.18m CMOS process. Simulation results show it can operate at clock frequencies from 10KHz to 50MHz. Average power for the patient with 75bpm heart rate is 13.34W