The Influence of ZnO Layer Thickness on the Performance and Electrical Bias Stress Instality in ZnO Thin Film Transistors

University of Buea supported the first author during the writing of this manuscript Open access articleThin Film Transistors (TFTs) are the active elements for future large area electronic applications, in which low cost, low temperature processes and optical transparency are required. Zinc oxide (ZnO) thin film transistors (TFTs) on SiO2/n+-Si substrate are fabricated with the channel thicknesses ranging from 20 nm to 60 nm. It is found that both the performance and gate bias stress related instabilities of the ZnO TFTs fabricated were influenced by the thickness of ZnO active channel layer. The effective mobility was found to improve with increasing ZnO thickness by up to an order in magnitude within the thickness range investigated (20 – 60 nm). However, thinner films were found to exhibit greater stability in threshold voltage and turn-on voltage shifts with respect to both positive and negative gate bias stress. It was also observed that both the turn on voltage (Von) and the threshold voltage (VT) decrease with increasing channel thickness. Moreover, the variations in subthreshold slope (S) with ZnO thickness as well as variations in VT and Von suggest a possible dependence of trap states in the ZnO on the ZnO thickness. This is further correlated by the dependence of VT and Von instabilities with gate bias stress

Silicon Nitride Deposition, Chromium Corrosion Mechanisms and Source/Drain Parasitic Resistance in Amorphous Silicon Thin Film transistors

Hydrogenated amorphous silicon (a-Si:H) based thin film transistors (TFTs) are finding increased application as switching elements in active-matrix liquid crystal displays (AMLCDs). Extensive research has been focussed on optimizing fabrication conditions to improve materials quality and on reducing channel length to increase device speed. However, the basic physics and chemistry have not yet been fully understood. In addition, little attention has been paid to the significant effect of source/drain parasitics. The work described in this thesis is closely related to the speed and stability issues on the discrete device level. Specifically, the influence of gate nitride deposition and its NH3 plasma treatment has been studied. The competing effects of nitridation reaction and radiation damage were found to cause an interesting trade-off between the device stability and speed. Further effort was devoted to the analysis of an important TFT failure phenomenon. Both electrical and spectroscopic techniques were utilized for gate Cr corrosion studies. It was determined that the corrosion was largely promoted by the CF4 plasma exposure of Cr during the fabrication. Finally, new test structures were designed, fabricated and characterized to study the source/drain parasitic resistance

Implant Activated Source/Drain Regions for Self-Aligned IGZO TFT

In this work, amorphous Indium Gallium Zinc Oxide (IGZO) TFTs with channel lengths scaled as small as L = 1 µm are presented which demonstrate excellent electrical characteristics, however the traditional metal-contact defined source/drain regions typically require several microns of gate overlap in order to provide ohmic behavior with minimal series resistance and ensure tolerance to overlay error. In addition, further scaling the channel length by simply reducing the source/drain metal gap is not feasible. The focus of this study is to investigate techniques to realize self-aligned (SA) IGZO TFTs that are not subject to gate-source/drain misalignment due to overlay error or process bias. Top gate (TG) co-planar and bottom gate (BG) staggered TFTs are fabricated using plasma immersion and ion implantation to selectively form conductive IGZO regions, with the channel region blocked by a gate-defined mask. Among the investigated treatments, oxygen plasma activation and ion implanted activation via 11B+ and 40Ar+ has been successfully demonstrated. Due to metal gate charging during ion implantation of SA-TG devices, the characteristics show a significant left-shift whereas SA-BG devices do not show this behavior. Electrical results suggest a defect-induced mechanism is involved with 40Ar+ implant activation of the S/D regions. However, 11B+ implant activation is attributed to the formation of an electrically active donor species involving chemical bonding. Both boron and argon demonstrate pronounced degradation in charge injection at higher dose treatments. Finally, a novel lithographic strategy which utilizes top-side flood exposure rather than a back-side through-glass exposure has also been explored, which would enable SA-BG devices on non-transparent substrates

Modeling 1/f noise in a-Si:H field-effect transistors

Hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) are used as switching elements in large area active matrix liquid crystal displays and various image sensing devices for radiation detection. The noise inherent in the a-Si:H TFTs contributes to the overall noise figure of such devices and degrades the signal to noise ratio; therefore, the noise is an important factor in the design of the devices. The noise of the a-Si:H TFTs has been studied experimentally, but the origin of the noise is not understood. This work calculates the noise of the a-Si:H TFTs based on a simulation of operation of the TFTs and the hypothesis that the device noise is due to the intrinsic noise of the a-Si:H material. An a-Si:H TFT with an inverted-staggered structure has been simulated by numerically solving the fundamental transport equations for various gate and drain-source voltages. The drain-source curves derived from the simulation agree qualitatively with the experimental results: both the linear and saturated regions are observed. The low frequency noise was calculated based on the charge density distribution in the channel obtained from the simulation and the known dependence of the noise in the a-Si:H on the charge density, Hooge’s relation. The calculated noise power increases with the drain-source voltage and is inversely proportional to the gate voltage or the effective channel length. The curves agree qualitatively with the experimental results. The calculated noise power agrees quantitatively with the experiments when the scaling parameter in Hooge’s relation, , is set to . This value agrees with the experimentally determined value for a-Si:H. The results are consistent with the hypothesis that the low frequency noise in the a-Si:H TFTs is due to the material itself

Critical Evaluation of Organic Thin-Film Transistor Models

Thin-film transistors (TFTs) represent a wide-spread tool to determine the charge-carrier mobility of materials. Mobilities and further transistor parameters like contact resistances are commonly extracted from the electrical characteristics. However, the trust in such extracted parameters is limited, because their values depend on the extraction technique and on the underlying transistor model. We propose a technique to establish whether a chosen model is adequate to represent the transistor operation. This two-step technique analyzes the electrical measurements of a series of TFTs with different channel lengths. The first step extracts the parameters for each individual transistor by fitting the full output and transfer characteristics to the transistor model. The second step checks whether the channel-length dependence of the extracted parameters is consistent with the model. We demonstrate the merit of the technique for distinct sets of organic TFTs that differ in the semiconductor, the contacts, and the geometry. Independent of the transistor set, our technique consistently reveals that state-of-the-art transistor models fail to reproduce the correct channel-length dependence. Our technique suggests that contemporary transistor models require improvements in terms of charge-carrier-density dependence of the mobility and/or the consideration of uncompensated charges in the transistor channel.Comment: 20 pages, 10 figure

Solution processed metal oxide microelectronics: from materials to devices

Owing to their many interesting characteristics, the application of metal oxide based electronics has been growing at a considerable rate for the past ten years. High performance, optical transparency, chemical stability and suitability toward low cost deposition methods make them well suited to a number of new and interesting application areas which conventional materials such as silicon, or more recently organic materials, are unable to satisfy.The work presented in this thesis is focussed on the optimisation of high performance metal oxide based electronics combined with use of spray pyrolysis, as a low cost deposition method. The findings presented here are split into three main areas, starting with an initial discussion on the physical and electronic properties of films deposited by spray pyrolysis. The results demonstrate a number of deposition criteria that aid in the optimisation and fabrication of high performance zinc oxide (ZnO) based thin-film transistors (TFTs) with charge carrier mobilities as high a 20 cm2/Vs. Solution processed gallium oxide TFTs with charge carrier mobilities of ~0.5 cm2/Vs are also demonstrated, highlighting the flexibility of the deposition method. The second part of the work explores the use of facile chemical doping methods suitable for spray pyrolysed ZnO based TFTs. By blending different precursor materials in solution prior to deposition, it has been possible to adjust certain material characteristics, and in turn device performance. Through the addition of lithium it has been possible alter the films grain structure, leading to significantly improved charge carrier mobilities as high as ~54 cm2/Vs. Additionally the inclusion of beryllium during film deposition has been demonstrated to control TFT threshold voltages, leading to improved integrated circuit performance. The final segment of work demonstrates the flexibility of spray pyrolysis through the deposition of a number of high-k dielectric materials. These high performance dielectrics are integrated into the fabrication of TFTs already benefiting from the findings of the previously discussed work, leading to highly optimised low-voltage TFTs. The performance of these devices represent some of best currently available from solution processed ZnO TFTs with charge carrier mobilities as high as 85 cm2/Vs operating at 3.5 V.Open Acces

Indium-Gallium-Zinc Oxide Thin-Film Transistors for Active-Matrix Flat-Panel Displays

Amorphous oxide semiconductors (AOSs) including amorphous InGaZnO (a-IGZO) areexpected to be used as the thin-film semiconducting materials for TFTs in the next-generation ultra-high definition (UHD) active-matrix flat-panel displays (AM-FPDs). a-IGZO TFTs satisfy almost all the requirements for organic light-emitting-diode displays (OLEDs), large and fast liquid crystal displays (LCDs) as well as three-dimensional (3D) displays, which cannot be satisfied using conventional amorphous silicon (a-Si) or polysilicon (poly-Si) TFTs. In particular, a-IGZO TFTs satisfy two significant requirements of the backplane technology: high field-effect mobility and large-area uniformity.In this work, a robust process for fabrication of bottom-gate and top-gate a-IGZO TFTs is presented. An analytical drain current model for a-IGZO TFTs is proposed and its validation is demonstrated through experimental results. The instability mechanisms in a-IGZO TFTs under high current stress is investigated through low-frequency noise measurements. For the first time, the effect of engineered glass surface on the performance and reliability of bottom-gate a-IGZO TFTs is reported. The effect of source and drain metal contacts on electrical properties of a-IGZO TFTs including their effective channel lengths is studied. In particular, a-IGZO TFTs with Molybdenum versus Titanium source and drain electrodes are investigated. Finally, the potential of aluminum substrates for use in flexible display applications is demonstrated by fabrication of high performance a-IGZO TFTs on aluminum substrates and investigation of their stability under high current electrical stress as well as tensile and compressive strain

\u3cem\u3eMaterials Integration and Device Fabrication of Active Matrix Thin Film Transistor Arrays for Intracellular Gene Delivery\u3c/em\u3e

Materials and process integration of a thin film transistor array for intra/extracellular probing are described in this study. A combinatorial rf magnetron sputter deposition technique was employed to investigate the electrical characteristics and micro-structural properties of molybdenum tungsten (MoW) high temperature electrodes as a function of the binary composition. In addition to the composition, the effect of substrate bias and temperature was investigated. The electrical resistivity of MoW samples deposited at room temperature with zero bias followed the typical Nordheim’s rule as a function of composition. The resistivity of samples deposited with substrate bias is uniformly lower and obeyed the rule of mixtures as a function of composition. The metastable β-W phase was not observed in the biased films even when deposited at room temperature. High resolution scanning electron microscopy revealed a more dense structure for the biased films, which correlated to the significantly lower film resistivity. In order to overcome deficiencies in sputtered silicon dioxide (SiO2) films the rf magnetron sputtering process was optimized by using a full factorial design of experiment (DOE). The optimized SiO2 film has a 5.7 MV/cm breakdown field and a 6.2 nm/min deposition rate at 10 W/cm2 RF power, 3 mTorr pressure, 300 °C substrate temperature, and 56 V substrate bias. Thin film transistors (TFTs) were also fabricated and characterized to show the prospective applications of the optimized SiO2 films. The effect that direct current (DC) substrate bias has on radio frequency (RF)-sputter-deposited amorphous silicon (a-Si) films was also investigated. The substrate bias produces a denser a-Si film with fewer defects compared to unbiased films. The reduced number of defects results in a higher resistivity because defect-mediated conduction paths are reduced. Thin film transistors (TFT) that were completely sputter-deposited were fabricated and characterized. The TFT with the biased a-Si film showed lower leakage (off-state) current, higher on/off current ratio, and higher transconductance (field effect mobility) than the TFT with the unbiased a-Si film. The crystallization properties of amorphous silicon (a-Si) thin film deposited by rf magnetron sputter deposition with substrate bias have been thoroughly characterized. The crystallization speed can be increased and the crystallization temperature can be drastically lowered relative to unbiased a-Si even though the stress state of biased a-Si film is highly compressive. The substrate bias enhances defect formation (vacancies, dislocations, stacking faults) via ion bombardment during the film growth, which effectively increases the driving force for crystallization of the films. The electrical and optical properties of sputter-deposited silicon nitride (SiNx) and n+ amorphous silicon (n+ a-Si) films as a function of substrate bias during sputter deposition were investigated. The breakdown voltage of sputter-deposited SiNx with 20 W (125 V) substrate bias is 7.65 MV/cm which is equivalent to that of plasma enhanced chemical vapor deposition (PECVD) SiNx films. The conductivity of n+ a-Si films are also enhanced by applying substrate bias during the sputter deposition. To verify the effect of substrate bias, amorphous silicon thin film transistors (TFTs) were fabricated with substrate biased thin films and compared their electrical properties with conventional sputter deposited TFTs. Lastly, electrochemical measurements were analyzed using gold and pyrrole solution to verify the active addressability of the TFT array fabricated by entirely by sputter deposited thin films below 200 °C temperature

New Application for Indium Gallium Zinc Oxide thin film transistors: A fully integrated Active Matrix Electrowetting Microfluidic Platform

The characterization and fabrication of active matrix TFTs [Thin Film Transistors] have been studied for applying an addressable microfluidic electrowetting channel device. The a-IGZO [Amorphous Indium Gallium Zinc Oxide] is used for electronic switching device to control the microfluidic device because of its high mobility, transparency, and easy to fabrication. The purpose of this dissertation is to optimize each IGZO TFT process including the optimization of a-IGZO properties to achieve robust device for application. To drive the IGZO TFTs, the channel resistance of IGZO layer and contact resistance between IGZO layer and source/drain (S/D) electrode are discussed in this dissertation. In addition, the generalization of IGZO sputter condition is investigated by calculation of IGZO and O2 [Oxygen] incorporation rate at different oxygen partial pressure and different sputter targets. To develop the robust IGZO TFTs, the different passivation layers deposited by RF [Radio Frequency] magnetron sputter are investigated by comparing the electrical characteristics of TFTs. The effects PECVD [Plasma Enhanced Chemical Vapor Deposition] of SiO2 [Silicon Dioxide] passivation layers on IGZO TFTs is studied the role of hydrogen and oxygen with analyzed and compared the concentration by the SIMS [Secondary Ion Mass Spectroscopy]. In addition, the preliminary electrowetting tests are performed for electrowetting phenomena, the liquid droplet actuation, the comparison between conventional electrowetting and Laplace barrier electrowetting, and the different size electrode effect for high functional properties. The active matrix addressing method are introduced and investigated for driving the electrowetting microfluidic channel device by Pspice simulation. Finally, the high resolution electrowetting microfluidic device (16ⅹ16 matrix) is demonstrated by driving liquid droplet and channel moving using active matrix addressing method and fully integrated IGZO TFTs