Dynamic reconfiguration technologies based on FPGA in software defined radio system

Partial Reconfiguration (PR) is a method for Field Programmable Gate Array (FPGA) designs which allows multiple applications to time-share a portion of an FPGA while the rest of the device continues to operate unaffected. Using this strategy, the physical layer processing architecture in Software Defined Radio (SDR) systems can benefit from reduced complexity and increased design flexibility, as different waveform applications can be grouped into one part of a single FPGA. Waveform switching often means not only changing functionality, but also changing the FPGA clock frequency. However, that is beyond the current functionality of PR processes as the clock components (such as Digital Clock Managers (DCMs)) are excluded from the process of partial reconfiguration. In this paper, we present a novel architecture that combines another reconfigurable technology, Dynamic Reconfigurable Port (DRP), with PR based on a single FPGA in order to dynamically change both functionality and also the clock frequency. The architecture is demonstrated to reduce hardware utilization significantly compared with standard, static FPGA design

A Review :Implementation of Reed Solomon Error Correction & Detec-tion For Wireless Network 802.16

The reed Solomon (255,239) are error-correcting & detecting code. Reed-Solomon codes are the most frequently used digital error control. It is also called as forword error code. The main part of reed-Solomon encoder is the linear feedback shift register that is implemented using VHDL A pipelined RS decoders is proposed of reducing the hardware complexity use the pipelined GFmultiplier in the syndrome computation block, KES block, Forney block, Chien search block and error correction block for provides low com-plexity the extended inversion less Massey-Berlekamp algorithm is used. The extended inversion less Massey-Berlekamp algorithm overcomes both the error locator polynomial and the error evaluator polynomial at the same time

AN OFDM platform for wireless systems testing: alamouti 2x1 MIMO example

In this paper, we present a real-time implementation of an OFDM hardware platform. The platform is based on HW blocks that can be put together to configure a wireless system based on OFDM modulation. The platform can be easily upgraded to test pre-coding cooperation algorithms. We evaluate the platform to implement a diversity Alamouti 2×1 MIMO scheme wireless system. The testbed is implemented using Field- Programmable Gate Array (FPGAs) through Xilinx System Generator for DSP. Blocks for time-domain synchronization and channel estimation are key components necessary in transmission system that require good time synchronization and channel estimation for efficient demodulation

HARDWARE IMPLEMENTATION OF MISO ON ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING PLATFORM WITH THE HELP OF ALAMOUTI ALGORITHM

Many software based OFDM techniques were proposed from last half decade to improve the performance of the system. This paper tried to implement the same with Hardware implementation. We created Hardware based MISO platform with OFDM. We implemented Alamouti algorithm on this test bed. The test bed is implemented with the help of Field Programmable Gate Array (FPGA). The test bed is functionalized with the help of FPGA through Xilinx based system generator for DSP. In this paper we considered the 2×1 MISO implementation with Alamouti algorithm. The simulation results showed that BER and SNR are considerably high for MISO than SISO. The results also proved that proposed OFDM based Alamouti implementation for MISO is excellent in all performance criterionsMany software based OFDM techniques were proposed from last half decade to improve the performance of the system. This paper tried to implement the same with Hardware implementation. We created Hardware based MISO platform with OFDM. We implemented Alamouti algorithm on this test bed. The test bed is implemented with the help of Field Programmable Gate Array (FPGA). The test bed is functionalized with the help of FPGA through Xilinx based system generator for DSP. In this paper we considered the 2×1 MISO implementation with Alamouti algorithm. The simulation results showed that BER and SNR are considerably high for MISO than SISO. The results also proved that proposed OFDM based Alamouti implementation for MISO is excellent in all performance criterion

A real-time FPGA-based implementation of a high-performance MIMO-OFDM mobile WiMAX transmitter

The Multiple Input Multiple Output (MIMO)-Orthogonal Frequency Division Multiplexing (OFDM) is considered a key technology in modern wireless-access communication systems. The IEEE 802.16e standard, also denoted as mobile WiMAX, utilizes the MIMO-OFDM technology and it was one of the first initiatives towards the roadmap of fourth generation systems. This paper presents the PHY-layer design, implementation and validation of a high-performance real-time 2x2 MIMO mobile WiMAX transmitter that accounts for low-level deployment issues and signal impairments. The focus is mainly laid on the impact of the selected high bandwidth, which scales the implementation complexity of the baseband signal processing algorithms. The latter also requires an advanced pipelined memory architecture to timely address the datapath operations that involve high memory utilization. We present in this paper a first evaluation of the extracted results that demonstrate the performance of the system using a 2x2 MIMO channel emulation.Postprint (published version

Design and development of mobile channel simulators using digital signal processing techniques

A mobile channel simulator can be constructed either in the time domain using a tapped delay line filter or in the frequency domain using the time variant transfer function of the channel. Transfer function modelling has many advantages over impulse response modelling. Although the transfer function channel model has been envisaged by several researchers as an alternative to the commonly employed tapped delay line model, so far it has not been implemented. In this work, channel simulators for single carrier and multicarrier OFDM system based on time variant transfer function of the channel have been designed and implemented using DSP techniques in SIMULINK. For a single carrier system, the simulator was based on Bello's transfer function channel model. Bello speculated that about 10Βτ(_MAX) frequency domain branches might result in a very good approximation of the channel (where в is the signal bandwidth and τ(_MAX) is the maximum excess delay of the multi-path channel). The simulation results showed that 10Bτ(_MAX) branches gave close agreement with the tapped delay line model(where Be is the coherence bandwidth). This number is π times higher than the previously speculated 10Bτ(_MAX).For multicarrier OFDM system, the simulator was based on the physical (PHY) layer standard for IEEE 802.16-2004 Wireless Metropolitan Area Network (WirelessMAN) and employed measured channel transfer functions at the 2.5 GHz and 3.5 GHz bands in the simulations. The channel was implemented in the frequency domain by carrying out point wise multiplication of the spectrum of OFDM time The simulator was employed to study BER performance of rate 1/2 and rate 3/4 coded systems with QPSK and 16-QAM constellations under a variety of measured channel transfer functions. The performance over the frequency selective channel mainly depended upon the frequency domain fading and the channel coding rate

EFFICIENT IMPLEMENTATION OF CHANNEL CODING AND INTERSPERSING IN MIMO-OFDM SYSTEMS

The standards for high speed data communications in wireless LAN and MAN such as Worldwide Interoperability for Microwave Access (Wi MAX) is mainly used by Orthogonal Frequency Division Multiplexing (OFDM). An analysis of the different channel coding and interleaving schemes is presented in this paper which is used in MIMO-OFDM systems. Based on the bit error rate (BER) performance and hardware implementation issues a comparison of these schemes is presented. An examination is done on the effects of four different types of channel coding and interleaving schemes which are being used. The Wi MAX or IEEE 802.16 is used as a reference for imitation, execution, and analysis. The cross-antenna coding and per-antenna interleaving systems perform better under all signals to noise ratio (SNR) conditions for all modulation schemes which is shown from the above coding and interleaving schemes which are studied. The data rates for IEEE 802.16 are doubled for 2x2 MIMO systems without using the transmit diversity using the proposed schemes

An FPGA implementation of OFDM transceiver for LTE applications

The paper presents a real-time transceiver using an Orthogonal Frequency-Division Multiplexing (OFDM) signaling scheme. The transceiver is implemented on a Field- Programmable Gate Array (FPGA) through Xilinx System Generator for DSP and includes all the blocks needed for the transmission path of OFDM. The transmitter frame can be reconfigured for different pilot and data schemes. In the receiver, time-domain synchronization is achieved thr ough a joint maximum likelihood (ML) symbol arrival-time and carrier frequency offset (CFO) estimator through the redundant information contained in the cyclic prefix (CP). A least-squares channel estimation retrieves the channel state information and a simple zero-forcing scheme has been implemented for channel equalization. Results show that a rough implementation of the signal path can be impleme nted by using only Xilinx System Generator for DSP