VHDL implementation and synthesis of adaptive thresholding

As the world of mobile multimedia computing continues to grow, so does the need for small, high performance, low power microchips. The implementation of the software algorithms used in these systems therefore has become an increasingly important issue in more recent applications. In order to realize the goals of our technological society and keep up with the speed at which computing technology is growing, the hardware implementation of these algorithms must be examined. This thesis describes the implementation and system simulation of four image binarization algorithms. The first algorithm is a simple global thresholding algorithm, while the remaining three adapt to the luminescent properties of the image. A high-level design philosophy was utilized throughout the course of the research. Each algorithm was first modeled in MATLAB, implemented and simulated in VHDL, and then synthesized to an FPGA where their operation was tested using a custom PC interface. High-level programming methods were used in both the modeling and VHDL implementations of the algorithms. The algorithms were synthesized to an Altera 20K200E FPGA on the Excalibur NIOS development board. Of the four algorithms, the local thresholding algorithm would not synthesize due to the high-level VHDL loop commands which were utilized in the implementation. The remaining three, global thresholding, running average thresholding, and quick adaptive thresholding were synthesized and written to the target device with 7.12%, 89.76% and 58.52% utilization of the devices on the FPGA respectively. The global thresholding algorithm achieved a clock frequency of 62.1 MHz, running thresholding achieved 17.6 MHz, and quick thresholding obtained a frequency of 21.4 MHz

Hierarchical N-Body problem on graphics processor unit

Galactic simulation is an important cosmological computation, and represents a classical N-body problem suitable for implementation on vector processors. Barnes-Hut algorithm is a hierarchical N-Body method used to simulate such galactic evolution systems. Stream processing architectures expose data locality and concurrency available in multimedia applications. On the other hand, there are numerous compute-intensive scientific or engineering applications that can potentially benefit from such computational and communication models. These applications are traditionally implemented on vector processors. Stream architecture based graphics processor units (GPUs) present a novel computational alternative for efficiently implementing such high-performance applications. Rendering on a stream architecture sustains high performance, while user-programmable modules allow implementing complex algorithms efficiently. GPUs have evolved over the years, from being fixed-function pipelines to user programmable processors. In this thesis, we focus on the implementation of Barnes-Hut algorithm on typical current-generation programmable GPUs. We exploit computation and communication requirements present in Barnes-Hut algorithm to expose their suitability for user-programmable GPUs. Our implementation of the Barnes-Hut algorithm is formulated as a fragment shader targeting the selected GPU. We discuss implementation details, design issues, results, and challenges encountered in programming the fragment shader

Development Of Information Visualization Methods For Use In Multimedia Applications

The aim of the article is development of a technique for visualizing information for use in multimedia applications. In this study, to visualize information, it is proposed first to compile a list of key terms of the subject area and create data tables. Based on the structuring of fragments of the subject area, a visual display of key terms in the form of pictograms, a visual display of key terms in the form of images, and a visual display of data tables are performed. The types of visual structures that should be used to visualize information for further use in multimedia applications are considered. The analysis of existing visual structures in desktop publishing systems and word processors is performed.To build a mechanism for visualizing information about the task as a presentation, a multimedia application is developed using Microsoft Visual Studio software, the C# programming language by using the Windows Forms application programming interface. An algorithm is proposed for separating pieces of information text that have key terms. Tabular data was visualized using the “parametric ruler” metaphorical visualization method, based on the metaphor of a slide rule.The use of the parametric ruler method on the example of data visualization for the font design of children's publications is proposed. Interaction of using the method is ensured due to the fact that the user will enter the size of the size that interests for it and will see the ratio of the values of other parameters. The practical result of the work is the creation of a multimedia application “Visualization of Publishing Standards” for the visualization of information for the font design of publications for children. The result of the software implementation is the finished multimedia applications, which, according to the standardization visualization technique in terms of prepress preparation of publications, is the final product of the third stage of the presentation of the visual for

On the Design of Perceptual MPEG-Video Encryption Algorithms

In this paper, some existing perceptual encryption algorithms of MPEG videos are reviewed and some problems, especially security defects of two recently proposed MPEG-video perceptual encryption schemes, are pointed out. Then, a simpler and more effective design is suggested, which selectively encrypts fixed-length codewords (FLC) in MPEG-video bitstreams under the control of three perceptibility factors. The proposed design is actually an encryption configuration that can work with any stream cipher or block cipher. Compared with the previously-proposed schemes, the new design provides more useful features, such as strict size-preservation, on-the-fly encryption and multiple perceptibility, which make it possible to support more applications with different requirements. In addition, four different measures are suggested to provide better security against known/chosen-plaintext attacks.Comment: 10 pages, 5 figures, IEEEtran.cl

The Design of a System Architecture for Mobile Multimedia Computers

This chapter discusses the system architecture of a portable computer, called Mobile Digital Companion, which provides support for handling multimedia applications energy efficiently. Because battery life is limited and battery weight is an important factor for the size and the weight of the Mobile Digital Companion, energy management plays a crucial role in the architecture. As the Companion must remain usable in a variety of environments, it has to be flexible and adaptable to various operating conditions. The Mobile Digital Companion has an unconventional architecture that saves energy by using system decomposition at different levels of the architecture and exploits locality of reference with dedicated, optimised modules. The approach is based on dedicated functionality and the extensive use of energy reduction techniques at all levels of system design. The system has an architecture with a general-purpose processor accompanied by a set of heterogeneous autonomous programmable modules, each providing an energy efficient implementation of dedicated tasks. A reconfigurable internal communication network switch exploits locality of reference and eliminates wasteful data copies

Design of multimedia processor based on metric computation

Media-processing applications, such as signal processing, 2D and 3D graphics rendering, and image compression, are the dominant workloads in many embedded systems today. The real-time constraints of those media applications have taxing demands on today's processor performances with low cost, low power and reduced design delay. To satisfy those challenges, a fast and efficient strategy consists in upgrading a low cost general purpose processor core. This approach is based on the personalization of a general RISC processor core according the target multimedia application requirements. Thus, if the extra cost is justified, the general purpose processor GPP core can be enforced with instruction level coprocessors, coarse grain dedicated hardware, ad hoc memories or new GPP cores. In this way the final design solution is tailored to the application requirements. The proposed approach is based on three main steps: the first one is the analysis of the targeted application using efficient metrics. The second step is the selection of the appropriate architecture template according to the first step results and recommendations. The third step is the architecture generation. This approach is experimented using various image and video algorithms showing its feasibility