Pilot-Based TI-ADC Mismatch Error Calibration for IR-UWB Receivers

In this work, we rst provide an overviewof the state of the art in mismatch error estimation and correction for time-interleaved analog to digital converters (TI-ADCs). Then, we present a novel pilot-based on-line adaptive timing mismatch error estimation approach for TI-ADCs in the context of an impulse radio ultra wideband (IR-UWB) receiver with correlation-based detection. We introduce the developed method and derive the expressions for both additive white Gaussian noise (AWGN) and Rayleigh multipath fading (RMPF) channels. We also derive a lower bound on the required ADC resolution to attain a certainestimation precision. Simulations show the effectiveness of the technique when combined with an adequate compensator. We analyze the estimation error behavior as a function of signal to noise ratio (SNR) and investigate the ADC performance before and after compensation. While all mismatches combined cause the effective number of bits (ENOB) to drop to 3 bits and to 6 bits when considering only timing mismatch, estimation and correction of these errors with the proposed technique can restore a close to ideal behavior.We also show the performance loss at the receiver in terms of bit error rate (BER) and how compensation is able to signicantly improve performance.Fil: Schmidt, Christian Andrés. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Figueroa, Jose Luis. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Cousseau, Juan Edmundo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Lopez Tonellotto, Mariana Andrea. University Of Klagenfurt; Austri

Pilot-Based TI-ADC Mismatch Error Calibration for IR-UWB Receivers

4openopenSchmidt C.A.; Figueroa J.L.; Cousseau J.E.; Tonello A.M.Schmidt, C. A.; Figueroa, J. L.; Cousseau, J. E.; Tonello, A. M

New iterative framework for frequency response mismatch correction in time-interleaved ADCs: Design and performance analysis

This paper proposes a new iterative framework for the correction of frequency response mismatch in time-interleaved analog-to-digital converters. Based on a general time-varying linear system model for the mismatch, we treat the reconstruction problem as a linear inverse problem and establish a flexible iterative framework for practical implementation. It encumbrances a number of efficient iterative correction algorithms and simplifies their design, implementation, and performance analysis. In particular, an efficient Gauss-Seidel iteration is studied in detail to illustrate how the correction problem can be solved iteratively and how the proposed structure can be efficiently implemented using Farrow-based variable digital filters with few general-purpose multipliers. We also study important issues, such as the sufficient convergence condition and reconstructed signal spectrum, derive new lower bound of signal-to-distortion-and-noise ratio in order to ensure stable operation, and predict the performance of the proposed structure. Furthermore, we propose an extended iterative structure, which is able to cope with systems involving more than one type of mismatches. Finally, the theoretical results and the effectiveness of the proposed approach are validated by means of computer simulations. © 2011 IEEE.published_or_final_versio

Accurate and efficient BER evaluation for high-speed OFDM systems impaired by TI-ADC circuit’s gain mismatch

This paper presents an efficient procedure to numerically evaluate the exact bit error rate of a rectangular quadrature amplitude modulated-orthogonal frequency division multiplexing (OFDM) system that is impaired by the gain mismatch of a time-interleaved analog-to-digital converter. As opposed to previous contributions, no approximations are involved in this procedure. The obtained results allow to accurately analyze the effect of this type of mismatch on the performance of practical high-speed OFDM systems. The accuracy and efficiency of the proposed technique are demonstrated by comparing analytical results with brute-force Monte-Carlo simulations

Estimation and Calibration Algorithms for Distributed Sampling Systems

Thesis Supervisor: Gregory W. Wornell Title: Professor of Electrical Engineering and Computer ScienceTraditionally, the sampling of a signal is performed using a single component such as an analog-to-digital converter. However, many new technologies are motivating the use of multiple sampling components to capture a signal. In some cases such as sensor networks, multiple components are naturally found in the physical layout; while in other cases like time-interleaved analog-to-digital converters, additional components are added to increase the sampling rate. Although distributing the sampling load across multiple channels can provide large benefits in terms of speed, power, and resolution, a variety mismatch errors arise that require calibration in order to prevent a degradation in system performance. In this thesis, we develop low-complexity, blind algorithms for the calibration of distributed sampling systems. In particular, we focus on recovery from timing skews that cause deviations from uniform timing. Methods for bandlimited input reconstruction from nonuniform recurrent samples are presented for both the small-mismatch and the low-SNR domains. Alternate iterative reconstruction methods are developed to give insight into the geometry of the problem. From these reconstruction methods, we develop time-skew estimation algorithms that have high performance and low complexity even for large numbers of components. We also extend these algorithms to compensate for gain mismatch between sampling components. To understand the feasibility of implementation, analysis is also presented for a sequential implementation of the estimation algorithm. In distributed sampling systems, the minimum input reconstruction error is dependent upon the number of sampling components as well as the sample times of the components. We develop bounds on the expected reconstruction error when the time-skews are distributed uniformly. Performance is compared to systems where input measurements are made via projections onto random bases, an alternative to the sinc basis of time-domain sampling. From these results, we provide a framework on which to compare the effectiveness of any calibration algorithm. Finally, we address the topic of extreme oversampling, which pertains to systems with large amounts of oversampling due to redundant sampling components. Calibration algorithms are developed for ordering the components and for estimating the input from ordered components. The algorithms exploit the extra samples in the system to increase estimation performance and decrease computational complexity

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

Adaptive Estimation and Compensation of the Time Delay in a Periodic Non-uniform Sampling Scheme

High sampling rate Analog-to-Digital Converters (ADCs) can be obtained by time-interleaving low rate (and thus low cost) ADCs into so-called Time-Interleaved ADCs (TI-ADCs). Nevertheless increasing the sampling frequency involves an increasing sensibility of the system to desynchronization between the different ADCs that leads to time-skew errors, impacting the system with non linear distortions. The estimation and compensation of these errors are considered as one of the main challenge to deal with in TI-ADCs. Some methods have been previously proposed, mainly in the field of circuits and systems, to estimate the time-skew error but they mainly involve hardware correction and they lack of flexibility, using an inflexible uniform sampling reference. In this paper, we propose to model the output of L interleaved and desynchronized ADCs with a sampling scheme called Periodic Non-uniform Sampling of order L (PNSL). This scheme has been initially proposed as an alternative to uniform sampling for aliasing cancellation, particularly in the case of bandpass signals. We use its properties here to develop a flexible on-line digital estimation and compensation method of the time delays between the desynchronized channels. The estimated delay is exploited in the PNSL reconstruction formula leading to an accurate reconstruction without hardware correction and without any need to adapt the sampling operation. Our method can be used in a simple Built-In Self-Test (BIST) strategy with the use of learning sequences and our model appears more flexible and less electronically expensive, following the principles of “Dirty Radio Frequency” paradigm: designing imperfect analog circuits with subsequently digital corrections of these imperfections

Adaptive Estimation and Compensation of the Time Delay in a Periodic Non-uniform Sampling Scheme

High sampling rate Analog-to-Digital Converters (ADCs) can be obtained by time-interleaving low rate (and thus low cost) ADCs into so-called Time-Interleaved ADCs (TI-ADCs). Nevertheless increasing the sampling frequency involves an increasing sensibility of the system to desynchronization between the different ADCs that leads to time-skew errors, impacting the system with non linear distortions. The estimation and compensation of these errors are considered as one of the main challenge to deal with in TI-ADCs. Some methods have been previously proposed, mainly in the field of circuits and systems, to estimate the time-skew error but they mainly involve hardware correction and they lack of flexibility, using an inflexible uniform sampling reference. In this paper, we propose to model the output of L interleaved and desynchronized ADCs with a sampling scheme called Periodic Non-uniform Sampling of order L (PNSL). This scheme has been initially proposed as an alternative to uniform sampling for aliasing cancellation, particularly in the case of bandpass signals. We use its properties here to develop a flexible on-line digital estimation and compensation method of the time delays between the desynchronized channels. The estimated delay is exploited in the PNSL reconstruction formula leading to an accurate reconstruction without hardware correction and without any need to adapt the sampling operation. Our method can be used in a simple Built-In Self-Test (BIST) strategy with the use of learning sequences and our model appears more flexible and less electronically expensive, following the principles of “Dirty Radio Frequency” paradigm: designing imperfect analog circuits with subsequently digital corrections of these imperfections

Time-Interleaved Analog-to-Digital-Converters: Modeling, Blind Identification and Digital Correction of Frequency Response Mismatches

Analog-to-digital-conversion enables utilization of digital signal processing (DSP) in many applications today such as wireless communication, radar and electronic warfare. DSP is the favored choice for processing information over analog signal processing (ASP) because it can typically offer more flexibility, computational power, reproducibility, speed and accuracy when processing and extracting information. Software defined radio (SDR) receiver is one clear example of this, where radio frequency waveforms are converted into digital form as close to the antenna as possible and all the processing of the information contained in the received signal is extracted in a configurable manner using DSP. In order to achieve such goals, the information collected from the real world signals, which are commonly analog in their nature, must be converted into digital form before it can be processed using DSP in the respective systems. The common trend in these systems is to not only process ever larger bandwidths of data but also to process data in digital format at ever higher processing speeds with sufficient conversion accuracy. So the analog-to-digital-converter (ADC), which converts real world analog waveforms into digital form, is one of the most important cornerstones in these systems.The ADC must perform data conversion at higher and higher rates and digitize ever-increasing bandwidths of data. In accordance with the Nyquist-Shannon theorem, the conversion rate of the ADC must be suffcient to accomodate the BW of the signal to be digitized, in order to avoid aliasing. The conversion rate of the ADC can in general be increased by using parallel ADCs with each ADC performing the sampling at mutually different points in time. Interleaving the outputs of each of the individual ADCs provides then a higher digitization output rate. Such ADCs are referred to as TI-ADC. However, the mismatches between the ADCs cause unwanted spurious artifacts in the TI-ADC’s spectrum, ultimately leading to a loss in accuracy in the TI-ADC compared to the individual ADCs. Therefore, the removal or correction of these unwanted spurious artifacts is essential in having a high performance TI-ADC system.In order to remove the unwanted interleaving artifacts, a model that describes the behavior of the spurious distortion products is of the utmost importance as it can then facilitate the development of efficient digital post-processing schemes. One major contribution of this thesis consists of the novel and comprehensive modeling of the spurious interleaving mismatches in different TI-ADC scenarios. This novel and comprehensive modeling is then utilized in developing digital estimation and correction methods to remove the mismatch induced spurious artifacts in the TI-ADC’s spectrum and recovering its lost accuracy. Novel and first of its kind digital estimation and correction methods are developed and tested to suppress the frequency dependent mismatch spurs found in the TI-ADCs. The developed methods, in terms of the estimation of the unknown mismatches, build on statistical I/Q signal processing principles, applicable without specifically tailored calibration signals or waveforms. Techniques to increase the analog BW of the ADC are also analyzed and novel solutions are presented. The interesting combination of utilizing I/Q downconversion in conjunction with TI-ADC is examined, which not only extends the TI-ADC’s analog BW but also provides flexibility in accessing the radio spectrum. Unwanted spurious components created during the ADC’s bandwidth extension process are also analyzed and digital correction methods are developed to remove these spurs from the spectrum. The developed correction techniques for the removal of the undesired interleaving mismatch artifacts are validated and tested using various HW platforms, with up to 1 GHz instantaneous bandwidth. Comprehensive test scenarios are created using measurement data obtained from HW platforms, which are used to test and evaluate the performance of the developed interleaving mismatch estimation and correction schemes, evidencing excellent performance in all studied scenarios. The findings and results presented in this thesis contribute towards increasing the analog BW and conversion rate of ADC systems without losing conversion accuracy. Overall, these developments pave the way towards fulfilling the ever growing demands on the ADCs in terms of higher conversion BW, accuracy and speed