Gate Delay Fault Test Generation for Non-Scan Circuits

This article presents a technique for the extension of delay fault test pattern generation to synchronous sequential circuits without making use of scan techniques. The technique relies on the coupling of TDgen, a robust combinational test pattern generator for delay faults, and SEMILET, a sequential test pattern generator for several static fault models. The approach uses a forward propagation-backward justification technique: The test pattern generation is started at the fault location, and after successful ¿local¿ test generation fault effect propagation is performed and finally a synchronising sequence to the required state is computed. The algorithm is complete for a robust gate delay fault model, which means that for every testable fault a test will be generated, assuming sufficient time. Experimental results for the ISCAS'89 benchmarks are presented in this pape

Testing asynchronous logic circuits from transistor networks to gate-level designs.

This dissertation is concerned with testing of asynchronous circuits. Asynchronous circuits are attracting increasing interest for future generations of high-speed low-power logic circuits because they facilitate concurrent computation, offer average-case performance and better technology migration potential, and eliminate clock skew. The research reported in this dissertation is a comprehensive study of testing asynchronous circuits using design-for-testability (DFT) techniques and test generation algorithms. In the first part of the study we propose an on-line DFT technique for detecting short defects (or IDDQ faults), which create a low-resistance path between the supply lines. It is shown that I DDQ testing, delay testing, and stuck-open testing are necessary in order to achieve a high defect coverage. The second DFT technique presented in this part is a novel circuit for concurrently detecting delay faults and stuck-open faults. In the proposed DFT techniques, in particular, fault detection in CMOS logic family is investigated. The second half of this study attempts to derive test sequences for sequential circuits. First, initialization phase is studied. Initialization is the process of driving the state signals in the circuit to known states. This dissertation presents an initialization technique for non-initializable asynchronous sequential circuits. Finally, we proceed by generating test sequences for asynchronous sequential circuits. We assume the presence of all multiple faults of all multiplicities. No faulty machines are generated during these procedures and we do not resort to their explicit enumeration.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1999 .R33. Source: Dissertation Abstracts International, Volume: 61-09, Section: B, page: 4897. Adviser: Majid Ahmadi. Thesis (Ph.D.)--University of Windsor (Canada), 1999

Convergence behaviour of structural FSM traversal

We present a theoretical analysis of structural FSM traversal, which is the basis for the sequential equivalence checking algorithm Record & Play presented earlier. We compare the convergence behaviour of exact and approximative structural FSM traversal with that of standard BDD-based FSM traversal. We show that for most circuits encountered in practice exact structural FSM traversal reaches the fixed point as fast as symbolic FSM traversal, while approximation can significantly reduce in the number of iterations needed. Our experiments confirm these results

Proof of finite surface code threshold for matching

The field of quantum computation currently lacks a formal proof of experimental feasibility. Qubits are fragile and sophisticated quantum error correction is required to achieve reliable quantum computation. The surface code is a promising quantum error correction code, requiring only a physically reasonable 2-D lattice of qubits with nearest neighbor interactions. However, existing proofs that reliable quantum computation is possible using this code assume the ability to measure four-body operators and, despite making this difficult to realize assumption, require that the error rate of these operator measurements is less than 10^-9, an unphysically low target. High error rates have been proved tolerable only when assuming tunable interactions of strength and error rate independent of distance, which is also unphysical. In this work, given a 2-D lattice of qubits with only nearest neighbor two-qubit gates, and single-qubit measurement, initialization, and unitary gates, all of which have error rate p, we prove that arbitrarily reliable quantum computation is possible provided p<7.4x10^-4, a target that many experiments have already achieved. This closes a long-standing open problem, formally proving the experimental feasibility of quantum computation under physically reasonable assumptions.Comment: 5 pages, 4 figures, published versio

On applying the set covering model to reseeding

The Functional BIST approach is a rather new BIST technique based on exploiting embedded system functionality to generate deterministic test patterns during BIST. The approach takes advantages of two well-known testing techniques, the arithmetic BIST approach and the reseeding method. The main contribution of the present paper consists in formulating the problem of an optimal reseeding computation as an instance of the set covering problem. The proposed approach guarantees high flexibility, is applicable to different functional modules, and, in general, provides a more efficient test set encoding then previous techniques. In addition, the approach shorts the computation time and allows to better exploiting the tradeoff between area overhead and global test length as well as to deal with larger circuits

Classically-Controlled Quantum Computation

Quantum computations usually take place under the control of the classical world. We introduce a Classically-controlled Quantum Turing Machine (CQTM) which is a Turing Machine (TM) with a quantum tape for acting on quantum data, and a classical transition function for a formalized classical control. In CQTM, unitary transformations and measurements are allowed. We show that any classical TM is simulated by a CQTM without loss of efficiency. The gap between classical and quantum computations, already pointed out in the framework of measurement-based quantum computation is confirmed. To appreciate the similarity of programming classical TM and CQTM, examples are given.Comment: 20 page

Program transformation for functional circuit descriptions

We model sequential synchronous circuits on the logical level by signal-processing programs in an extended lambda calculus Lpor with letrec, constructors, case and parallel or (por) employing contextual equivalence. The model describes gates as (parallel) boolean operators, memory using a delay, which in turn is modeled as a shift of the list of signals, and permits also constructive cycles due to the parallel or. It opens the possibility of a large set of program transformations that correctly transform the expressions and thus the represented circuits and provides basic tools for equivalence testing and optimizing circuits. A further application is the correct manipulation by transformations of software components combined with circuits. The main part of our work are proof methods for correct transformations of expressions in the lambda calculus Lpor, and to propose the appropriate program transformations

Instrument for determining coincidence and elapse time between independent sources of random sequential events

An instrument that receives pulses from a primary external source and one or more secondary external sources and determines when there is coincidence between the primary and one of the secondary sources is described. The instrument generates a finite time window (coincidence aperture) during which coincidence is defined to have occurred. The time intervals between coincidence apertures in which coincidences occur are measured