Implementation of Viterbi decoder on Xilinx XC4005XL FPGA

The Viterbi decoding algorithm is used to decode convolutional codes and is found in many systems that receive digital data that might contain errors. The use of error-correcting codes has proven tobe an effective way to overcome data corruption in digital communication channels. In previous works, researchers describe the Viterbi Algorithm, but the accuracy does not exceed 10% of data points. Also, a lot of previous works do not follow IEEE 802.16 new specifications. Viterbi decoders are generally implemented using programmable digital signal processors (DSPs) or special purpose chip sets and application-specific integrated circuits (ASICs). Here, we aim to implement such decoder on an FPGA. In This paper, we provide a more accurate Viterbi decoder according to IEEE 802.16 specifications. We used VHDL hardware description language to implement the algorithm. We also used OrCAD Capture V9.1 to compile, synthesize, and simulate our code. IEEE 802.16 standard specifies the air interface of fixed point-to-multipoint broadband wireless access (BWA) systems providing multiple services. This standard is intended to enable rapid worldwide deployment of broadband wireless access products. The new IEEE 802.16 specifications require a Viterbi block decoder with constraint length of 3, traceback length of 32, and minimum throughput requirement of 44.8 Mbps. The Implementation parameters for the decoder have been determined through simulation and the decoder has been implemented on a Xilinx XC4005XL FPGA

HDMI/DVI interface implementation into FPGA chip

Práce se zabývá implementací rozhraní pro přenos digitálních video signálů do obvodu FPGA. Jsou zde popsány technické specifikace rozhraní HDMI a DVI. Teoretická část je zaměřena na popis standardu TMDS, který definuje přenos video signálu, a na popis logiky TMDS vysílače a přijímače. Druhá část práce se zabývá vytvořeným softwarovým jádrem a jsou zde uvedeny výsledky z testování. K testování softwarového jádra je použita vývojová deska s FPGA obvodem Spartan-6.This work focuses on the implementation of interface for transmission of digital video signals in the FPGA. The thesis includes technical specifications for HDMI and DVI. Theoretical part deals with the TMDS standard, which defines the broadcasting of the video signal, and describes the TMDS transmitter logic. The second part then focuses on the constructed IP core and includes the testing results. Development board with FPGA Spartan-6 was used for testing.

The AutoProof Verifier: Usability by Non-Experts and on Standard Code

Formal verification tools are often developed by experts for experts; as a result, their usability by programmers with little formal methods experience may be severely limited. In this paper, we discuss this general phenomenon with reference to AutoProof: a tool that can verify the full functional correctness of object-oriented software. In particular, we present our experiences of using AutoProof in two contrasting contexts representative of non-expert usage. First, we discuss its usability by students in a graduate course on software verification, who were tasked with verifying implementations of various sorting algorithms. Second, we evaluate its usability in verifying code developed for programming assignments of an undergraduate course. The first scenario represents usability by serious non-experts; the second represents usability on "standard code", developed without full functional verification in mind. We report our experiences and lessons learnt, from which we derive some general suggestions for furthering the development of verification tools with respect to improving their usability.Comment: In Proceedings F-IDE 2015, arXiv:1508.0338

Specifying Reusable Components

Reusable software components need expressive specifications. This paper outlines a rigorous foundation to model-based contracts, a method to equip classes with strong contracts that support accurate design, implementation, and formal verification of reusable components. Model-based contracts conservatively extend the classic Design by Contract with a notion of model, which underpins the precise definitions of such concepts as abstract equivalence and specification completeness. Experiments applying model-based contracts to libraries of data structures suggest that the method enables accurate specification of practical software

Modal logics for reasoning about object-based component composition

Component-oriented development of software supports the adaptability and maintainability of large systems, in particular if requirements change over time and parts of a system have to be modified or replaced. The software architecture in such systems can be described by components and their composition. In order to describe larger architectures, the composition concept becomes crucial. We will present a formal framework for component composition for object-based software development. The deployment of modal logics for defining components and component composition will allow us to reason about and prove properties of components and compositions

The pros and cons of using SDL for creation of distributed services

In a competitive market for the creation of complex distributed services, time to market, development cost, maintenance and flexibility are key issues. Optimizing the development process is very much a matter of optimizing the technologies used during service creation. This paper reports on the experience gained in the Service Creation projects SCREEN and TOSCA on use of the language SDL for efficient service creation

Validate implementation correctness using simulation: the TASTE approach

High-integrity systems operate in hostile environment and must guarantee a continuous operational state, even if unexpected events happen. In addition, these systems have stringent requirements that must be validated and correctly translated from high-level specifications down to code. All these constraints make the overall development process more time-consuming. This becomes especially complex because the number of system functions keeps increasing over the years. As a result, engineers must validate system implementation and check that its execution conforms to the specifications. To do so, a traditional approach consists in a manual instrumentation of the implementation code to trace system activity while operating. However, this might be error-prone because modifications are not automatic and still made manually. Furthermore, such modifications may have an impact on the actual behavior of the system. In this paper, we present an approach to validate a system implementation by comparing execution against simulation. In that purpose, we adapt TASTE, a set of tools that eases system development by automating each step as much as possible. In particular, TASTE automates system implementation from functional (system functions description with their properties – period, deadline, priority, etc.) and deployment(processors, buses, devices to be used) models. We tailored this tool-chain to create traces during system execution. Generated output shows activation time of each task, usage of communication ports (size of the queues, instant of events pushed/pulled, etc.) and other relevant execution metrics to be monitored. As a consequence, system engineers can check implementation correctness by comparing simulation and execution metrics