Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed

Maximum-likelihood estimation of delta-domain model parameters from noisy output signals

Fast sampling is desirable to describe signal transmission through wide-bandwidth systems. The delta-operator provides an ideal discrete-time modeling description for such fast-sampled systems. However, the estimation of delta-domain model parameters is usually biased by directly applying the delta-transformations to a sampled signal corrupted by additive measurement noise. This problem is solved here by expectation-maximization, where the delta-transformations of the true signal are estimated and then used to obtain the model parameters. The method is demonstrated on a numerical example to improve on the accuracy of using a shift operator approach when the sample rate is fast

Maximally flat and least-square co-design of variable fractional delay filters for wideband software-defined radio

This paper describes improvements in a Farrow-structured variable fractional delay (FD) Lagrange filter for all-pass FD interpolation. The main idea is to integrate the truncated sinc into the Farrow structure of a Lagrange filter, in order that a superior FD approximation in the least-square sense can be achieved. Its primary advantages are the lower level of mean-square-error (MSE) over the whole FD range and the reduced implementation cost. Extra design parameters are introduced for making the trade-off between MSE and maximal flatness under different design requirements. Design examples are included, illustrating an MSE reduction of 50% compared to a classical Farrow-structured Lagrange interpolator while the implementation cost is reduced. This improved variable FD interpolation system is suitable for many applications, such as sample rate conversion, digital beamforming and timing synchronization in wideband software-defined radio (SDR) communications

AREA AND POWER-EFFICIENT RECONFIGURABLE DIGITAL DOWN CONVERTER ON FPGA

This paper presents a field-programmable gate array (FPGA)-based digital down converter (DDC) that can reduce the bandwidth from about 70 MHz to 182.292 kHz. The proposed DDC consists of a polyphase COordinate Rotation DIgital Computer (CORDIC) processor and a multirate filter. The advantage of polyphase CORDIC processor is to process with high sample rate input data and produces computational efficient noiseless baseband spectrum. The pipeline multirate filter works at a high clock speed. Moreover, the multirate filter generates a fractional sample rate factor using a cubic B-spline Farrow filter. The proposed DDC is coded with optimal hardware description language (HDL) and tested on Kintex-7 Xilinx FPGA as the target device. Experimental results indicate that the proposed design saves chip area, power consumption and operates at high speed without loss of any functionality. Additionally, the proposed design offers sufficient spurious-free dynamic range (SFDR) and produces less than 1 Hz frequency resolution at the output

A versatile iterative framework for the reconstruction of bandlimited signals from their nonuniform samples

In this paper, we study a versatile iterative framework for the reconstruction of uniform samples from nonuniform samples of bandlimited signals. Assuming the input signal is slightly oversampled, we first show that its uniform and nonuniform samples in the frequency band of interest can be expressed as a system of linear equations using fractional delay digital filters. Then we develop an iterative framework, which enables the development and convergence analysis of efficient iterative reconstruction algorithms. In particular, we study the Richardson iteration in detail to illustrate how the reconstruction problem can be solved iteratively, and show that the iterative method can be efficiently implemented using Farrow-based variable digital filters with few general-purpose multipliers. Under the proposed framework, we also present a completed and systematic convergence analysis to determine the convergence conditions. Simulation results show that the iterative method converges more rapidly and closer to the true solution (i.e. the uniform samples) than conventional iterative methods using truncation of sinc series. © 2010 The Author(s).published_or_final_versionSpringer Open Choice, 21 Feb 201

Efficient 1D and circular symmetric 2D FIR filters with variable cutoff frequencies using the Farrow structure and multiplier-block

IEEE International Symposium on Circuits and Systems, Sydney, NSW, Australia, 6-9 May 2001This paper proposes new structures for realizing 1D and circular symmetric 2D FIR filters with variable cutoff frequencies. They are based on the interpolation of the impulse responses using the Farrow structure. The coefficients of the sub-filters in the Farrow structure are represented in sum-of-powers-of-two (SOPOT) coefficients, which can easily be implemented as simple shifts and additions. Furthermore, using the transposed form realization of the sub-filters, all the SOPOT coefficients can be implemented by a single multiplier-block exploiting the redundancy among the SOPOT coefficients. Several design examples are given to demonstrate the effectiveness and feasibility of the proposed approach.published_or_final_versio