Indirect test of M-S circuits using multiple specification band guarding

Testing analog and mixed-signal circuits is a costly task due to the required test time targets and high end technical resources. Indirect testing methods partially address these issues providing an efficient solution using easy to measure CUT information that correlates with circuit performances. In this work, a multiple specification band guarding technique is proposed as a method to achieve a test target of misclassified circuits. The acceptance/rejection test regions are encoded using octrees in the measurement space, where the band guarding factors precisely tune the test decision boundary according to the required test yield targets. The generated octree data structure serves to cluster the forthcoming circuits in the production testing phase by solely relying on indirect measurements. The combined use of octree based encoding and multiple specification band guarding makes the testing procedure fast, efficient and highly tunable. The proposed band guarding methodology has been applied to test a band-pass Butterworth filter under parametric variations. Promising simulation results are reported showing remarkable improvements when the multiple specification band guarding criterion is used.Peer ReviewedPostprint (author's final draft

Optimizing Frequency Channels for Adults with Cochlear Implants

Cochlear implants (CIs) are devices used by individuals with hearing loss to improve communication through the use of an electrode array that directly stimulates the auditory nerve. Existing signal processing strategies utilize a logarithmic frequency-to-electrode allocation, mimicking the representation of frequencies along the basilar membrane (high frequencies at the base and low frequencies at the apex). These strategies support some degree of open-set speech recognition for CI users; however, average speech recognition remains well below what normal-hearing adults are capable of. To enhance speech recognition in adult CI users, this study examined one promising alternative to the standard logarithmic frequency-to-electrode allocation maps. The frequency-to-electrode allocation maps were modified to provide more refined representations of the first two (and most important) vowel formant frequencies (energy peaks in vowels that are critical to speech perception). Twelve participants were tested using two different CI maps: one based on existing clinical frequency-to-electrode allocation strategies (Standard) and one designed to improve the resolution of the first two formants, which should especially enhance vowel recognition (Speech). Alternating between these maps, participants listened to and repeated three kinds of stimulus materials: (1) highly meaningful five-word sentences, (2) syntactically correct but not meaningful four-word sentences, and (3) phonetically balanced consonant-vowel-consonant words in isolation. Analyses revealed that some participants benefitted from the Speech strategy. Moreover, an improvement in vowel recognition in words strongly predicted an improvement in recognition of words in sentences. These findings suggest that optimizing the representation of the first two formants enhances speech recognition for CI users. Future efforts should focus on better representing this speech-specific information in modern-day signal processing strategies.No embargoAcademic Major: Speech and Hearing Scienc

Role of homeostasis in learning sparse representations

Neurons in the input layer of primary visual cortex in primates develop edge-like receptive fields. One approach to understanding the emergence of this response is to state that neural activity has to efficiently represent sensory data with respect to the statistics of natural scenes. Furthermore, it is believed that such an efficient coding is achieved using a competition across neurons so as to generate a sparse representation, that is, where a relatively small number of neurons are simultaneously active. Indeed, different models of sparse coding, coupled with Hebbian learning and homeostasis, have been proposed that successfully match the observed emergent response. However, the specific role of homeostasis in learning such sparse representations is still largely unknown. By quantitatively assessing the efficiency of the neural representation during learning, we derive a cooperative homeostasis mechanism that optimally tunes the competition between neurons within the sparse coding algorithm. We apply this homeostasis while learning small patches taken from natural images and compare its efficiency with state-of-the-art algorithms. Results show that while different sparse coding algorithms give similar coding results, the homeostasis provides an optimal balance for the representation of natural images within the population of neurons. Competition in sparse coding is optimized when it is fair. By contributing to optimizing statistical competition across neurons, homeostasis is crucial in providing a more efficient solution to the emergence of independent components

A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multi-core neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.Comment: 17 pages, 14 figure