A Unifying Framework for Finite Wordlength Realizations.

A general framework for the analysis of the finite wordlength (FWL) effects of linear time-invariant digital filter implementations is proposed. By means of a special implicit system description, all realization forms can be described. An algebraic characterization of the equivalent classes is provided, which enables a search for realizations that minimize the FWL effects to be made. Two suitable FWL coefficient sensitivity measures are proposed for use within the framework, these being a transfer function sensitivity measure and a pole sensitivity measure. An illustrative example is presented

System-level optimization of baseband filters for communication applications

In this paper, a design approach for the high-level synthesis of programmable continuous-time baseband filters able to achieve optimum trade-off among dynamic range, distortion behavior, mismatch tolerance and power area consumptions is presented. The proposed approach relies on building programming circuit elements as arrays of switchable unit cells and defines the synthesis as a constrained optimization problem with both continuous and discrete variables, this last representing the number of enabled cells of the arrays at each configuration. The cost function under optimization is, then, defined as a weighted combination of performance indices which are estimated from macromodels of the circuit elements. The methodology has been implemented in MATLAB™ and C++, and covers all the classical approximation techniques for filters, most common circuit topologies (namely, ladder simulation and cascaded biquad realizations) and both transconductance-C (Gm-C) and active-RC implementation approaches. The proposed synthesis strategy is illustrated with a programmable equal-ripple ladder Gm-C filter for a multi-band power-line communication modem.P.R.O.F.I.T. FIT-070000-2001-84

Verification of Magnitude and Phase Responses in Fixed-Point Digital Filters

In the digital signal processing (DSP) area, one of the most important tasks is digital filter design. Currently, this procedure is performed with the aid of computational tools, which generally assume filter coefficients represented with floating-point arithmetic. Nonetheless, during the implementation phase, which is often done in digital signal processors or field programmable gate arrays, the representation of the obtained coefficients can be carried out through integer or fixed-point arithmetic, which often results in unexpected behavior or even unstable filters. The present work addresses this issue and proposes a verification methodology based on the digital-system verifier (DSVerifier), with the goal of checking fixed-point digital filters w.r.t. implementation aspects. In particular, DSVerifier checks whether the number of bits used in coefficient representation will result in a filter with the same features specified during the design phase. Experimental results show that errors regarding frequency response and overflow are likely to be identified with the proposed methodology, which thus improves overall system's reliability

Order bound for the realization of a combination of positive filters

In a problem on the realization of digital ¯lters, initiated by Gersho and Gopinath [8], we extend and complete a remarkable result of Benvenuti, Farina and Anderson [4] on decomposing the transfer function t(z) of an arbitrary linear, asymptotically stable, discrete, time-invariant SISO system as a di®erence t(z) = t1(z) ¡ t2(z) of two positive, asymptotically stable linear systems. We give an easy-to-compute algorithm to handle the general problem, in particular, also the case of transfer functions t(z) with multiple poles, which was left open in [4]. One of the appearing positive, asymptotically stable systems is always 1-dimensional, while the other has dimension depending on the order and, in the case of nonreal poles, also on the location of the poles of t(z). The appearing dimension is seen to be minimal in some cases and it can always be calculated before carrying out the realization

Optimal realizations of floating-point implemented digital controllers with finite word length considerations.

The closed-loop stability issue of finite word length (FWL) realizations is investigated for digital controllers implemented in floating-point arithmetic. Unlike the existing methods which only address the effect of the mantissa bits in floating-point implementation to the sensitivity of closed-loop stability, the sensitivity of closed-loop stability is analysed with respect to both the mantissa and exponent bits of floating-point implementation. A computationally tractable FWL closed-loop stability measure is then defined, and the method of computing the value of this measure is given. The optimal controller realization problem is posed as searching for a floating-point realization that maximizes the proposed FWL closed-loop stability measure, and a numerical optimization technique is adopted to solve for the resulting optimization problem. Simulation results show that the proposed design procedure yields computationally efficient controller realizations with enhanced FWL closed-loop stability performance

Optimal Controller and Filter Realisations using Finite-precision, Floating- point Arithmetic.

The problem of reducing the fragility of digital controllers and filters implemented using finite-precision, floating-point arithmetic is considered. Floating-point arithmetic parameter uncertainty is multiplicative, unlike parameter uncertainty resulting from fixed-point arithmetic. Based on first- order eigenvalue sensitivity analysis, an upper bound on the eigenvalue perturbations is derived. Consequently, open-loop and closed-loop eigenvalue sensitivity measures are proposed. These measures are dependent upon the filter/ controller realization. Problems of obtaining the optimal realization with respect to both the open-loop and the closed-loop eigenvalue sensitivity measures are posed. The problem for the open-loop case is completely solved. Solutions for the closed-loop case are obtained using non-linear programming. The problems are illustrated with a numerical example

On Out-of-Band Emissions of Quantized Precoding in Massive MU-MIMO-OFDM

We analyze out-of-band (OOB) emissions in the massive multi-user (MU) multiple-input multiple-output (MIMO) downlink. We focus on systems in which the base station (BS) is equipped with low-resolution digital-to-analog converters (DACs) and orthogonal frequency-division multiplexing (OFDM) is used to communicate to the user equipments (UEs) over frequency-selective channels. We demonstrate that analog filtering in combination with simple frequency-domain digital predistortion (DPD) at the BS enables a significant reduction of OOB emissions, but degrades the signal-to-interference-noise-and-distortion ratio (SINDR) at the UEs and increases the peak-to-average power ratio (PAR) at the BS. We use Bussgang's theorem to characterize the tradeoffs between OOB emissions, SINDR, and PAR, and to study the impact of analog filters and DPD on the error-rate performance of the massive MU-MIMO-OFDM downlink. Our results show that by carefully tuning the parameters of the analog filters, one can achieve a significant reduction in OOB emissions with only a moderate degradation of error-rate performance and PAR.Comment: Presented at the 2017 Asilomar Conference on Signals, Systems, and Computers, 6 page

Fractionally-addressed delay lines

While traditional implementations of variable-length digital delay lines are based on a circular buffer accessed by two pointers, we propose an implementation where a single fractional pointer is used both for read and write operations. On modern general-purpose architectures, the proposed method is nearly as efficient as the popularinterpolated circular buffer, and it behaves well for delay-length modulations commonly found in digital audio effects. The physical interpretation of the new implementation shows that it is suitable for simulating tension or density modulations in wave-propagating media.Comment: 11 pages, 19 figures, to be published in IEEE Transactions on Speech and Audio Processing Corrected ACM-clas

SMT-Based Bounded Model Checking of Fixed-Point Digital Controllers

Digital controllers have several advantages with respect to their flexibility and design's simplicity. However, they are subject to problems that are not faced by analog controllers. In particular, these problems are related to the finite word-length implementation that might lead to overflows, limit cycles, and time constraints in fixed-point processors. This paper proposes a new method to detect design's errors in digital controllers using a state-of-the art bounded model checker based on satisfiability modulo theories. The experiments with digital controllers for a ball and beam plant demonstrate that the proposed method can be very effective in finding errors in digital controllers than other existing approaches based on traditional simulations tools