Configurable multiple value encoders using semi floating-gate

This thesis presents a new multiple-valued encoder with re-configurable radix. The proposed circuits utilize serial cyclic D/A conversion and semi floatinggate (SFG) inverters for compact design and a high functional capacity per device. A re-configurable radix is not supported by existing SFG inverter based multiple-valued encoders which make use of parallel binary weight D/A conversion. The study covers least significant bit-first (LSB), least significant bit-first with alternate bit inversion (LSB ABI) and most significant bit-first (MSB) digital input codes. The serial cyclic D/A converters with LSB and LSB ABI input codes are implemented in a double-poly 0.35um AMS process. Measured results are provided and analyzed using standard static D/A converter performance measures. Circuits are tested using the practical radices 4, 8 and 16. Experimental results demonstrate that serial cyclic D/A converters using SFG inverters are feasible. Compared to related work on cyclic D/A conversion, the proposed circuits feature both a reduced number of devices and a reduction in the required die area. Several new techniques are identified for extending the resolution beyond radix 4, 8 and 16 MVL applications. This includes an error correction algorithm called least significant bit-first with alternate bit inversion (LSB ABI), a sample and hold clock scheme and a Dual Data-Rate (DDR) mode of D/A converter operation. The techniques are implemented on a chip and measured results are provided. The thesis also includes simulation work on several new SFG based circuits. A ternary serial D/A converter, a MSB-first serial D/A converter and a multiple-valued frequency divider which features re-configurable modulus

INTEGRATED SINGLE-PHOTON SENSING AND PROCESSING PLATFORM IN STANDARD CMOS

Practical implementation of large SPAD-based sensor arrays in the standard CMOS process has been fraught with challenges due to the many performance trade-offs existing at both the device and the system level [1]. At the device level the performance challenge stems from the suboptimal optical characteristics associated with the standard CMOS fabrication process. The challenge at the system level is the development of monolithic readout architecture capable of supporting the large volume of dynamic traffic, associated with multiple single-photon pixels, without limiting the dynamic range and throughput of the sensor. Due to trade-offs in both functionality and performance, no general solution currently exists for an integrated single-photon sensor in standard CMOS single photon sensing and multi-photon resolution. The research described herein is directed towards the development of a versatile high performance integrated SPAD sensor in the standard CMOS process. Towards this purpose a SPAD device with elongated junction geometry and a perimeter field gate that features a large detection area and a highly reduced dark noise has been presented and characterized. Additionally, a novel front-end system for optimizing the dynamic range and after-pulsing noise of the pixel has been developed. The pixel is also equipped with an output interface with an adjustable pulse width response. In order to further enhance the effective dynamic range of the pixel a theoretical model for accurate dead time related loss compensation has been developed and verified. This thesis also introduces a new paradigm for electrical generation and encoding of the SPAD array response that supports fully digital operation at the pixel level while enabling dynamic discrete time amplitude encoding of the array response. Thus offering a first ever system solution to simultaneously exploit both the dynamic nature and the digital profile of the SPAD response. The array interface, comprising of multiple digital inputs capacitively coupled onto a shared quasi-floating sense node, in conjunction with the integrated digital decoding and readout electronics represents the first ever solid state single-photon sensor capable of both photon counting and photon number resolution. The viability of the readout architecture is demonstrated through simulations and preliminary proof of concept measurements

NP domino logic gates for Ultra Low Voltage and High Speed applications

In this thesis we present different configurations of digital circuits exploiting Ultra Low Voltage (ULV) NP domino logic style. The proposed logic style is utilized with the help of Floating gate transistors. The proposed NP domino logic gates are aimed to perform high speed operations in Ultra Low Voltage applications. The presented circuits may operate near the sub-threshold regime where the supply voltage is near the threshold voltage of the transistors. In terms of frequency, speed, robustness, Power Delay Product (PDP) and Energy Delay Product (EDP), the proposed ULV NP domino logic gates may offer significant improvement compared to the conventional CMOS logic gates. Different implementations of NOT, NAND and NOR gates are presented using both conventional and Pass Transistor Logic styles. Further, NAND and NOR gates are used to employ different configurations of Carry gates which is a speed limited factor in many arithmetic operations. These ULV NP domino Carry gates are simulated at different supply voltages in the range of 100mV to 400mV, and the performance results are presented with respect to delay, power, PDP and EDP. The proposed ULV NP domino Carry gates are cascaded together to perform addition in a 32-bit chain. The circuits are operated with respect to worst case scenario where the carry signal propagates through the whole chain. Multi-threshold (MTCMOS) and Variable-threshold (VTCMOS) techniques are employed in the ULV domino 32-bit carry chain in order to reduce the power consumption, meanwhile offering superb speed performance. Although the 32-bit carry chain offers a great advantage of speed improvement in the worst case scenario, the chain also introduces the drawback of enormous power consumption in the idle mode. The work in this thesis has resulted in three papers. Two of these papers represent various configurations of 1-bit ULV NP domino Carry gates, while the third paper examines the performance of one of the proposed ULV NP domino Carry gates in a 32-bit chain. The simulation results presented in this thesis are obtained using a 90nm TSMC CMOS process

Wireless Transceivers for Implantable Microsystems.

In this thesis, we present the first-ever fully integrated mm3 low-power biomedical transceiver with 1 meter of range that is powered by a mm2 thin-film battery. The transceiver is targeted for biomedical implants where size and energy constraints dictated by application make design challenging. Despite all the previous work in RFID tags, form factor of such radios is incompatible with mm3 biomedical implants. The proposed transceiver bridges this gap by providing a compact low-power solution that can run off small thin-film batteries and can be stacked with other system components in a 3D fashion. On the sensor-to-external side, we proposed a novel FSK architecture based on dual-resonator LC oscillators to mitigate unwanted overlap of two FSK tones’ phase noise spectrum. Due to inherent complexity of such systems, fourth order dual-resonator oscillators can exhibit instable operation. We mathematically modeled the instability and derive design conditions for stable oscillations. Through simulation and measurements, validity of derived models was confirmed. Together with other low-power system blocks, the transmitter was successfully implanted in live mouse and in-vivo measurements were performed to confirm successful transmission of vital signals through organic tissue. The integrated transmitter achieved a bit-error-rate of 10-6 at 10cm with 4.7nJ/bit energy consumption. On the external-to-sensor link, we proposed a new protocol to lower receiver peak power, which is highly limited due to small size of mm3 microsystem battery. In the proposed protocol, sending same data multiple times drastically relaxes jitter requirement on the sensor side at the cost of increased power consumption on the external side without increasing peak power radiated by the external unit. The receiver also uses a dual-coil LNA to improve range by 22% with only 11% area overhead. An asynchronous controller manages protocol timing and limits total monitoring current to 43nA. The fabricated receiver consumes 1.6nJ/bit at 40kbps while positioned 1m away from a 2W source.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/102458/1/ghaed_1.pd

Low Cost Earth Sensor Based on Oxygen Airglow (AIRES)

This project has demonstrated the feasibility of a low-cost Earth sensor based on imaging oxygen airglow, allowing 0.4° accuracy from GEO under any illumination condition. Available Earth Sensor (ES) are based on the measurement of the earth’s infrared radiation to determine the vector to the Earth’s centre. These designs provide excellent accuracies over a large field of view, but are often heavy, large, require cooling or temperature stabilization and are power hungry. In addition, the sensor concept for a LEO or GEO application ES differs significantly. We have developed a novel ES concept for applications where milli-degree accuracy is not required, but where low-cost is essential and lower (about 1 – 5°) accuracy is acceptable. Such a sensor could be used in new scenarios and to improve spacecraft reliability by providing a low-cost back-up sensor. Our Earth Sensor concept is based on imaging atmospheric oxygen emission at 762 nm using highly sensitive detectors. In both night-time and daytime there is continuous emission at 762 nm due to oxygen recombination. Low-noise active pixel sensors (APS) or low-light detector based on arrays of single photon avalanche diodes (SPAD) enables the ES to operate at night and day, over a wide temperature range, with a very compact optical system (aperture of 8 mm, focal length of 11 mm) and no scanning elements. A modular design allows designing similar instruments using the same wavelength band, the same detector technology, the same optics, the same power and data interfaces and similar algorithms for GEO and LEO applications, thus reducing the development cost. We have developed an Earth appearance model at 762 nm, which was used as input for the mechanical, optical and electric design of the Earth Sensor (conceptual design). In order to achieve a low-cost solution, simplicity and reduction of part count was a driving factor in the design trade-offs. Total mass for the GEO design is 845 g with a mean power consumption of 4 W. Algorithms were developed to determine the vector to the Earth from the images. A breadboard was built to display a simulated picture of the Earth under varying conditions, image those pictures at different temperatures with a radiation tolerant APS (LCMS), and verify the correct operation of the algorithms. In addition to the conceptual design and breadboard level demonstration of key technologies, a novel detector chip was designed and fabricated: a radiation-tolerant array of single photon avalanche photodiodes (SPAD) build using conventional 0.35 μm CMOS technology. The chip was tested under proton and gamma irradiation, and operated with only minor changes in dark current after 30 krad TID. Having shown the feasibility of such an Earth Sensor, this work concluded with a development plan to lead to a flight model

Photodetectors

In this book some recent advances in development of photodetectors and photodetection systems for specific applications are included. In the first section of the book nine different types of photodetectors and their characteristics are presented. Next, some theoretical aspects and simulations are discussed. The last eight chapters are devoted to the development of photodetection systems for imaging, particle size analysis, transfers of time, measurement of vibrations, magnetic field, polarization of light, and particle energy. The book is addressed to students, engineers, and researchers working in the field of photonics and advanced technologies

Low power circuits and systems for wireless neural stimulation

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 155-161).Electrical stimulation of tissues is an increasingly valuable tool for treating a variety of disorders, with applications including cardiac pacemakers, cochlear implants, visual prostheses, deep brain stimulators, spinal cord stimulators, and muscle stimulators. Brain implants for paralysis treatments are increasingly providing sensory feedback via neural stimulation. Within the field of neuroscience, the perturbation of neuronal circuits wirelessly in untethered, freely-behaving animals is of particular importance. In implantable systems, power consumption is often the limiting factor in determining battery or power coil size, cost, and level of tissue heating, with stimulation circuitry typically dominating the power budget of the entire implant. Thus, there is strong motivation to improve the energy efficiency of implantable electrical stimulators. In this thesis, I present two examples of low-power tissue stimulators. The first type is a wireless, low-power neural stimulation system for use in freely behaving animals. The system consists of an external transmitter and a miniature, implantable wireless receiver-and-stimulator utilizing a custom integrated chip built in a standard 0.5 ptm CMOS process. Low power design permits 12 days of continuous experimentation from a 5 mAh battery, extended by an automatic sleep mode that reduces standby power consumption by 2.5x. To test this device, bipolar stimulating electrodes were implanted into the songbird motor nucleus HVC of zebra finches. Single-neuron recordings revealed that wireless stimulation of HVC led to a strong increase of spiking activity in its downstream target, the robust nucleus of the arcopallium (RA). When this device was used to deliver biphasic pulses of current randomly during singing, singing activity was prematurely terminated in all birds tested. The second stimulator I present is a novel, energy-efficient electrode stimulator with feedback current regulation. This stimulator uses inductive storage and recycling of energy based on a dynamic power supply to drive an electrode in an adiabatic fashion such that energy consumption is minimized. Since there are no explicit current sources or current limiters, wasteful energy dissipation across such elements is naturally avoided. The stimulator also utilizes a shunt current-sensor to monitor and regulate the current through the electrode via feedback, thus enabling flexible and safe stimulation. The dynamic power supply allows efficient transfer of energy both to and from the electrode, and is based on a DC-DC converter topology that is used in a bidirectional fashion. In an exemplary electrode implementation, I show how the stimulator combines the efficiency of voltage control and the safety and accuracy of current control in a single low-power integrated-circuit built in a standard 0.35 pm CMOS process. I also perform a theoretical analysis of the energy efficiency that is in accord with experimental measurements. In its current proof-of-concept implementation, this stimulator achieves a 2x-3x reduction in energy consumption as compared to a conventional current-source-based stimulator operating from a fixed power supply.by Scott Kenneth Arfin.Ph.D

Ultrafast Radiographic Imaging and Tracking: An overview of instruments, methods, data, and applications

Ultrafast radiographic imaging and tracking (U-RadIT) use state-of-the-art ionizing particle and light sources to experimentally study sub-nanosecond dynamic processes in physics, chemistry, biology, geology, materials science and other fields. These processes, fundamental to nuclear fusion energy, advanced manufacturing, green transportation and others, often involve one mole or more atoms, and thus are challenging to compute by using the first principles of quantum physics or other forward models. One of the central problems in U-RadIT is to optimize information yield through, e.g. high-luminosity X-ray and particle sources, efficient imaging and tracking detectors, novel methods to collect data, and large-bandwidth online and offline data processing, regulated by the underlying physics, statistics, and computing power. We review and highlight recent progress in: a.) Detectors; b.) U-RadIT modalities; c.) Data and algorithms; and d.) Applications. Hardware-centric approaches to U-RadIT optimization are constrained by detector material properties, low signal-to-noise ratio, high cost and long development cycles of critical hardware components such as ASICs. Interpretation of experimental data, including comparisons with forward models, is frequently hindered by sparse measurements, model and measurement uncertainties, and noise. Alternatively, U-RadIT makes increasing use of data science and machine learning algorithms, including experimental implementations of compressed sensing. Machine learning and artificial intelligence approaches, refined by physics and materials information, may also contribute significantly to data interpretation, uncertainty quantification and U-RadIT optimization.Comment: 51 pages, 31 figures; Overview of ultrafast radiographic imaging and tracking as a part of ULITIMA 2023 conference, Mar. 13-16,2023, Menlo Park, CA, US