14,498 research outputs found
Photonics design tool for advanced CMOS nodes
Recently, the authors have demonstrated large-scale integrated systems with
several million transistors and hundreds of photonic elements. Yielding such
large-scale integrated systems requires a design-for-manufacture rigour that is
embodied in the 10 000 to 50 000 design rules that these designs must comply
within advanced complementary metal-oxide semiconductor manufacturing. Here,
the authors present a photonic design automation tool which allows automatic
generation of layouts without design-rule violations. This tool is written in
SKILL, the native language of the mainstream electric design automation
software, Cadence. This allows seamless integration of photonic and electronic
design in a single environment. The tool leverages intuitive photonic layer
definitions, allowing the designer to focus on the physical properties rather
than on technology-dependent details. For the first time the authors present an
algorithm for removal of design-rule violations from photonic layouts based on
Manhattan discretisation, Boolean and sizing operations. This algorithm is not
limited to the implementation in SKILL, and can in principle be implemented in
any scripting language. Connectivity is achieved with software-defined
waveguide ports and low-level procedures that enable auto-routing of waveguide
connections.Comment: 5 pages, 10 figure
Self-aligned silicidation of surround gate vertical MOSFETs for low cost RF applications
We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high drive-current vertical devices. Silicided 80-nm vertical n-channel devices fabricated using 0.5-?m lithography are compared with nonsilicided devices. A source–drain (S/D) activation anneal of 30 s at 1100 ?C is shown to deliver a channel length of 80 nm, and the silicidation gives a 60% improvement in drive current in comparison with nonsilicided devices. The silicided devices exhibit a subthreshold slope (S) of 87 mV/dec and a drain-induced barrier lowering (DIBL) of 80 mV/V, compared with 86 mV/dec and 60 mV/V for nonsilicided devices. S-parameter measurements on the 80-nm vertical nMOS devices give an fT of 20 GHz, which is approximately two times higher than expected for comparable lateral MOSFETs fabricated using the same 0.5-?m lithography. Issues associated with silicidation down the pillar sidewall are investigated by reducing the activation anneal time to bring the silicided region closer to the p-n junction at the top of the pillar. In this situation, nonlinear transistor turn-on is observed in drain-on-top operation and dramatically degraded drive current in source-on-top operation. This behavior is interpreted using mixed-mode simulations, which show that a Schottky contact is formed around the perimeter of the pillar when the silicided contact penetrates too close to the top S/D junction down the side of the pillar
A Memristor as Multi-Bit Memory: Feasibility Analysis
The use of emerging memristor materials for advanced electrical devices such as multi-valued logic is expected to outperform today's binary logic digital technologies. We show here an example for such non-binary device with the design of a multi-bit memory. While conventional memory cells can store only 1 bit, memristors-based multi-bit cells can store more information within single device thus increasing the information storage density. Such devices can potentially utilize the non-linear resistance of memristor materials for efficient information storage. We analyze the performance of such memory devices based on their expected variations in order to determine the viability of memristor-based multi-bit memory. A design of read/write scheme and a simple model for this cell, lay grounds for full integration of memristor multi-bit memory cell
Static and dynamic characterization of pull-in protected CMOS compatible poly-SiGe grating light valves
status: publishe
Recommended from our members
CMOS design enhancement techniques for RF receivers. Analysis, design and implementation of RF receivers with component enhancement and component reduction for improved sensitivity and reduced cost, using CMOS technology.
Silicon CMOS Technology is now the preferred process for low power wireless
communication devices, although currently much noisier and slower than comparable
processes such as SiGe Bipolar and GaAs technologies. However, due to ever-reducing
gate sizes and correspondingly higher speeds, higher Ft CMOS processes are
increasingly competitive, especially in low power wireless systems such as Bluetooth,
Wireless USB, Wimax, Zigbee and W-CDMA transceivers. With the current 32 nm gate
sized devices, speeds of 100 GHz and beyond are well within the horizon for CMOS
technology, but at a reduced operational voltage, even with thicker gate oxides as
compensation.
This thesis investigates newer techniques, both from a systems point of view and at a
circuit level, to implement an efficient transceiver design that will produce a more
sensitive receiver, overcoming the noise disadvantage of using CMOS Silicon. As a
starting point, the overall components and available SoC were investigated, together
with their architecture.
Two novel techniques were developed during this investigation. The first was a high
compression point LNA design giving a lower overall systems noise figure for the
receiver. The second was an innovative means of matching circuits with low Q
components, which enabled the use of smaller inductors and reduced the attenuation
loss of the components, the resulting smaller circuit die size leading to smaller and
lower cost commercial radio equipment. Both these techniques have had patents filed by the
University.
Finally, the overall design was laid out for fabrication, taking into account package
constraints and bond-wire effects and other parasitic EMC effects
A review of advances in pixel detectors for experiments with high rate and radiation
The Large Hadron Collider (LHC) experiments ATLAS and CMS have established
hybrid pixel detectors as the instrument of choice for particle tracking and
vertexing in high rate and radiation environments, as they operate close to the
LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for
which the tracking detectors will be completely replaced, new generations of
pixel detectors are being devised. They have to address enormous challenges in
terms of data throughput and radiation levels, ionizing and non-ionizing, that
harm the sensing and readout parts of pixel detectors alike. Advances in
microelectronics and microprocessing technologies now enable large scale
detector designs with unprecedented performance in measurement precision (space
and time), radiation hard sensors and readout chips, hybridization techniques,
lightweight supports, and fully monolithic approaches to meet these challenges.
This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog.
Phy
- …