Assessment of a Surface Water Supply for Source and Treated Distribution System Quality

This study focused on providing a source to tap assessment of surface water systems with respect to (i) the use of alternative biomonitoring tools, (ii) disinfection byproduct (DBP) formation and control, and (iii) corrosion control. In the first study component, two water systems were microbiologically evaluated using adenosine triphosphate (ATP) bioluminescence technology. It was determined that microbial ATP was useful as a surrogate for biomonitoring within a surface water system when paired with traditional methods. Although microbial activity differed between distribution systems that used either chloramine or chlorine disinfectant, in both cases flowrate and season affected microbial ATP values. In the second study component, total trihalomethanes (TTHM) and haloacetic acids (HAA5) DBP formation and disinfectant stability was investigated using a novel DBP control process. The method relied on a combination of sulfate, ultraviolet light irradiation, pH, and aeration unit operations. Results indicate respective decreases in 7-day TTHM and HAA5 formation potentials of 36% - 57% and 20% - 47% for the surface waters investigated. In the third component of this work, a corrosion study assessed the effect of disinfectant chemical transitions on the corrosion rates of common distribution system metals. When a chlorine based disinfection system transitioned between chlorine and chloramine, mild steel corrosion increased by 0.45 mils per year (mpy) under chloramine and returned to baseline corrosion rates under chlorine. However, when a chloramine based disinfection system transitioned between chloramine and chlorine, mild steel corrosion increased in tandem with total chlorine levels. Unlike the chlorine system, the mild steel corrosion rates did not return to baseline under chloramine after exposure to 5 mg/L of total chlorine. Surface water systems should consider the use of ATP as a surrogate for biomonitoring, consider the novel treatment process for DBP formation control, and consider corrosion control in disinfectant decision-making activities

Automatic surface defect quantification in 3D

Three-dimensional (3D) non-contact optical methods for surface inspection are of significant interest to many industrial sectors. Many aspects of manufacturing processes have become fully automated resulting in high production volumes. However, this is not necessarily the case for surface defect inspection. Existing human visual analysis of surface defects is qualitative and subject to varying interpretation. Automated 3D non-contact analysis should provide a robust and systematic quantitative approach. However, different 3D optical measurement technologies use different physical principles, interact with surfaces and defects in diverse ways, leading to variation in measurement data. Instrument s native software processing of the data may be non-traceable in nature, leading to significant uncertainty about data quantisation. Sub-millimetric level surface defect artefacts have been created using Rockwell and Vickers hardness testing equipment on various substrates. Four different non-contact surface measurement instruments (Alicona InfiniteFocus G4, Zygo NewView 5000, GFM MikroCAD Lite and Heliotis H3) have been utilized to measure different defect artefacts. The four different 3D optical instruments are evaluated by calibrated step-height created using slipgauges and reference defect artefacts. The experimental results are compared to select the most suitable instrument capable of measuring surface defects in robust manner. This research has identified a need for an automatic tool to quantify surface defect and thus a mathematical solution has been implemented for automatic defect detection and quantification (depth, area and volume) in 3D. A simulated defect softgauge with a known geometry has been developed in order to verify the implemented algorithm and provide mathematical traceability. The implemented algorithm has been identified as a traceable, highly repeatable, and high speed solution to quantify surface defect in 3D. Various industrial components with suspicious features and solder joints on PCB are measured and quantified in order to demonstrate applicability

Shape Memory Alloy Reinforced Self-healing Metal Matrix Composites

A metal matrix composite system incorporating Nickel Titanium (NiTi) Shape Memory Alloy (SMA) as smart reinforcement with self-healing potential for crack closure is investigated. Lead free proof of concept solder matrix-alloys of Sn-Bi with off eutectic compositions were designed, synthesized and characterized. This was aimed at enabling partial melting of the matrix at healing temperature - the temperature at which the reinforced SMA reverts to its original shape, whereby welding the cracks shut. In this composite system, NiTi long fibers (wires) have been incorporated as reinforcements. The reinforcements were etched and flux treated to improve wettability with the solder matrix and enhance the fiber matrix interface strength. This was followed by dip coating the fiber with matrix alloy and pressure infiltration of the Single Fiber Composites (SFCs) thus obtained to get a high volume fraction of the reinforcement in the resulting composite. Microscopic characterization of the matrix and interface via optical and scanning electron microscopy followed by electrical and mechanical testing of the composite was undertaken. Etching and fluxing with subsequent Pressure infiltration of SFCs to get self-healing composites was demonstrated as a viable method of synthesizing self-healing composites. Finally, macroscopic shape recovery and healing of the microstructure were demonstrated in the obtained samples. Complete crack closure evaluated by metallography of cross-section for Bi-10%Sn/NiTi with 23% liquid (eutectic) at a healing temperature of 145˚C was achieved, with the eutectic melting and sealing the crack. Complete recovery of flexural strain was observed in all bent samples. 92% of flexural strength was recovered for Sn-20% Bi /NiTi composite and 88% of the strength was recovered for Bi-10% Sn/NiTi composite within an hour of healing

Micro-mechanical characteristics and dimensional change of Cu-Sn interconnects due to growth of interfacial intermetallic compounds

Sn-based solder alloys are extensively used in electronic devices to form interconnects between different components to provide mechanical support and electrical path. The formation of a reliable solder interconnects fundamentally relies on the metallurgic reaction between the molten solder and solid pad metallization in reflowing. The resultant IMC layer at the solder/pad metallization interface can grow continuously during service or aging at an elevated temperature, uplifting the proportion of IMCs in the entire solder joint. However, the essential mechanical properties of interfacial IMC (i.e. Cu6Sn5, Cu3Sn) layers, such as Young s modulus and hardness, are drastically different in comparison with Sn-based solder and substrate. Therefore, the increasing fraction of interfacial IMCs in the solder joint can lead to significant deformation incompatibility under exterior load, which becomes an important reliability concern in the uses of solder joints for electronic interconnects. In the past decades, extensive research works were implemented and reported regarding the growth of interfacial IMC layers and its effect on the mechanical integrity of solder joints. But, the following fundamental issues in terms of mechanical and microstructural evolution in the uses of solder joints still remain unclear, demanding further research to elaborate: (1) The protrusion of IMCs: Though the growth of interfacial IMC layers along the diffusion direction in solder joints were studied extensively, the growth of IMCs perpendicular to the diffusion direction were reported in only a few papers without any further detailed investigation. This phenomena can crucially govern the long-term reliability of solder interconnects, in particular, in the applications that require a robust microstructural integrity from a solder joint. (2) Fracture behaviour of interfacial IMC layers: The fracture behaviour of interfacial IMC layers is a vital factor in determining the failure mechanism of solder joints, but this was scarcely investigated due to numerous challenges to enable a potential in-situ micro-scale tests. It is therefore highly imperative to carry out such study in order to reveal the fracture behaviour of interfacial IMC layers which can eventually provide better understanding of the influence of interfacial IMC layers on the mechanical integrity of solder joints. (3) Volume shrinkage: The volume shrinkage (or solder joint collapse) induced by the growth of interfacial IMC layers was frequently ascribed as one of the main causes of the degradation of mechanical reliability during aging due to the potentially resulted voids and residual stress at the solder/substrate interface. However, very few experimental works on the characterisation of such type of volume shrinkage can be found in literatures, primarily due to the difficulties of observing the small dimensional changes that can be encountered in the course of IMCs growth. (4) Residual stress: The residual stress within solder joints is another key factor that contributes to the failure of solder joints under external loads. However, the stress evolution in solder joints as aging progresses and the potential correlation between the residual stress and the growth of interfacial IMC layers is yet to be fully understood, as stress/strain status can fundamentally alter the course of total failure of a solder joint. (5) Crack initiation and propagation in solder joints: Modelling on the mechanical behaviour of solder joints is often undertaken primarily on the stress distribution within solder joints, for instance, under a given external loading. But there is lack of utilising numerical analysis to simulate the crack initiation and propagation within solder joints, thus the effect of interfacial IMC layers on the fracture behaviour of the solder joints can be elaborated in further details. In this thesis, the growth of interfacial IMCs in parallel and perpendicular to the interdiffusion direction in the Sn99Cu1/Cu solder joints after aging was investigated and followed by observation with SEM, with an intention of correlating the growth of IMCs along these two directions with aging durations based on the measured thickness of IMC layer and height of perpendicular IMCs. The mechanism of the protrusion of IMCs and the mutual effect between the growth of IMCs along these two directions was also discussed. The tensile fracture behaviour of interfacial Cu6Sn5 and Cu3Sn layers at the Sn99Cu1/Cu interface was characterised by implementing cantilever bending tests on micro Cu6Sn5 and Cu3Sn pillars prepared by focused ion beam (FIB). The fracture stress and strain were evaluated by finite element modelling using Abaqus. The tensile fracture mechanism of both Cu6Sn5 and Cu3Sn can then be proposed and discussed based on the observed fracture surface of the micro IMC pillars. The volume shrinkage of solder joints induced by the growth of interfacial IMC layers in parallel to the interdiffusion direction in solder joint was also studied by specifically designed specimens, to enable the collapse of the solder joint to be estimated by surface profiling with Zygo Newview after increased durations of aging. Finite element modelling was also carried out to understand the residual stress potentially induced due to the volume shrinkage. The volume shrinkage in solder joints is likely to be subjected to the constraint from both the attached solder and substrate, which can lead to the build-up of residual stress at the solder/Cu interface. Depth-controlled nanoindentation tests were therefore carried out in the Sn99Cu1 solder, interfacial Cu6Sn5 layer, Cu3Sn layer and Cu with Vickers indenter after aging. The residual stress was then evaluated in the correlation with aging durations, different interlayers and the locations in the solder joint. Finally, finite element models incorporated with factors that may contribute to the failure of solder joints, including microstructure of solder joints, residual stress and the fracture of interfacial IMC, were built using Abaqus to reveal the effect of these factors on the fracture behaviour of solder joints under applied load. The effect of growth of IMC layer during aging on the fracture behaviour was then discussed to provide a better understanding of the degradation of mechanical integrity of solder joints due to aging. The results from this thesis can facilitate the understanding of the influence of interfacial IMC layers on the mechanical behaviour of solder joints due to long-term exposure to high temperatures

Development of a Rapid Fatigue Life Testing Method for Reliability Assessment of Flip-Chip Solder Interconnects

The underlying physics of failure are critical in assessing the long term reliability of power packages in their intended field applications, yet traditional reliability determination methods are largely inadequate when considering thermomechanical failures. With current reliability determination methods, long test durations, high costs, and a conglomerate of concurrent reliability degrading threat factors make effective understanding of device reliability difficult and expensive. In this work, an alternative reliability testing apparatus and associated protocol was developed to address these concerns; targeting rapid testing times with minimal cost while preserving fatigue life prediction accuracy. Two test stands were fabricated to evaluate device reliability at high frequency (60 cycles/minute) with the first being a single-directional unit capable of exerting large forces (up to 20 N) on solder interconnects in one direction. The second test stand was developed to allow for bi-directional application of stress and the integration of an oven to enable testing at elevated steady-state temperatures. Given the high frequency of testing, elevated temperatures are used to emulate the effects of creep on solder fatigue lifetime. Utilizing the mechanical force of springs to apply shear loads to solder interconnects within the devices, the reliability of a given device to withstand repeated cycling was studied using resistance monitoring techniques to detect the number of cycles-to-failure (CTF). Resistance monitoring was performed using specially designed and fabricated, device analogous test vehicles assembled with the ability to monitor circuit resistance in situ. When a resistance rise of 30 % was recorded, the device was said to have failed. A mathematical method for quantifying the plastic work density (amount of damage) sustained by the solder interconnects prior to failure was developed relying on the relationship between Hooke’s Law for springs and damage deflection to accurately assess the mechanical strength of tested devices

Process Development of FlexTrate(TM) Connector for Silicon Interconnect Fabric

Heterogeneous integration is emerging as the mainstay in the performance and scaling enhancement trend. At the Center for Heterogeneous Integration and Performance Scaling (CHIPS), University of California, Los Angeles (UCLA), Silicon Interconnect Fabric (Si-IF) has been established as a heterogeneous wafer-scale integration technology, where bare dies can be mounted on silicon wafer directly with the advantages like fine pitch, small inter-die spacing, lower latency, and higher data bandwidth. As an external communication system for Si-IF, FR4-based periphery connector was investigated earlier but it still has issues such as, CTE mismatch and poor flexibility. To address this problem, Flextrate(TM) Connector, a novel flexible device, is proposed. FlexTrate(TM) is a flexible hybrid packaging platform using fan-out wafer-level packaging method to heterogeneously integrate dies in polydimethylsiloxane (PDMS) substrate. In this thesis, FlexTrate(TM) technology is used to fabricate copper wires on PDMS substrate to form a connector that can serve as an external communication system for Si-IF with better mechanical properties, such as better elongation and lower Young’s modulus

ISPET: Interface Sintering Process Enhanced Technology

The research presented in this thesis was carried out in VISHAY Semiconductor Italiana S.P.A. at Borgaro Torinese - Italy. The framework of this thesis is the study of new materials for power electronics application, analysing their thermal, mechanical and electrical properties. Emerging application of high power systems requires new methods for power electronics integration and packaging. Stringent requirements in size and weight, reliability, durability, ambient and operation temperatures are pushing to go beyond the limits in industrial applications. As a consequence, our studies are focused on power modules, incorporating new materials and technology processes (sintering) for dies or chips (silicon), substrates and interconnection materials (wire bonding). This thesis work starts introducing the power semiconductor devices used in power electronics and their integration on Power Integrated Circuits (low and medium power density) and Power Modules (medium, high and very high power density). This chapter will explain technology evolution, power semiconductor device utilization mode and some applications. Chapter 2 will be focused on power modules packages. They have an important role for providing cooling, electrical connection and correct insulation, between the internal semiconductor devices and the external circuit. Isolated and non isolated packages are analysed and compared. Chapter 3 will make a point on the methods of thermal characterization and reliability tests, that were implemented to evaluate the impact of the introduction of new materials and processes into the device. In chapter 4, first experimental results, related to the sintering process will be discussed. In this chapter the attention will be focused on the Chip to substrate Joint of the device, analysing methods to mechanically fix die to substrate. The sintering process will be treated, analysing the process and the results will be thermally and mechanically characterized. The chapter 5 will present the experimental part oriented to the combinations of materials to produce a better heavy wire bonding, supported by a Design of Experiments (DOE). The behaviour of didifferent wires will be compared through thermal characterization methods and reliability test

Fundamental study of underfill void formation in flip chip assembly

Flip Chip in Package (FCIP) has been developed to achieve the assembly process with area array interconnects. Particularly, a high I/O count coupled with finer pitch area array interconnects structured FCIP can be achieved using no-flow underfill assembly process. Using the assembly process, a high, stable yield assembly process recently reported with eutectic lead-tin solder interconnections, 150 µm pitch, and I/O counts in excess of 3000. The assembly process reported created a large number of voids among solder interconnects in FCIP. The voids formed among solder interconnections can propagate, grow, and produce defects such as solder joint cracking and solder bridging. Moreover, these voids can severely reduce reliability performance. Indeed, many studies were conducted to examine the void formation in FCIP. Based on the studies, flip chip geometric design, process conditions, and material formulation have been considered as the potential causes of void formation. However, the present research won't be able to identify the mechanism of void formation, causing a lot of voids in assembly process without consideration of chemical reaction in the assembly process with a fine-pitch, high I/O density FCIP. Therefore, this research will present process technology necessary to achieve high yields in FCIP assemblies using no-flow underfills and investigate the underlying problem of underfill void formation in these assemblies. The plausible causes of void formation will be investigated using experimental techniques. The techniques will identify the primary source of the void formation. Besides, theoretical models will be established to predict the number of voids and to explain the growth behavior of voids in the FCIP. The established theoretical models will be verified by experiments. These models will validate with respect to the relationship between process parameters to achieve a high yield and to minimize voids in FCIP assemblies using no-flow underfill materials regarding process as well as material stand points. Eventually, this research provides design guideline achieving a high, stable yield and void-free assembly process.Ph.D.Committee Chair: Baldwin, Daniel; Committee Member: Colton, Jonathan; Committee Member: Ghiaasiaan, Mostafa; Committee Member: Moon, Jack; Committee Member: Tummala, Ra