New processing techniques for large-area electronics

Recent advancements in the semiconductor industry have been driven by the extreme downscaling of device dimensions enabled by innovative photolithography methods. However, such nano-scale patterning technologies are impractical for large-area electronics primarily due to extremely high cost and incompatibility with large-area processing. Therefore, alternative techniques that are simpler, more scalable and compatible with large-area manufacturing are required. This thesis explores the technological potential of two recently developed patterning techniques namely interlayer lithography (IL) and adhesion-lithography (a-Lith) for application in the field of large-area nano/electronics. The IL method relies on the use of a pre-patterned metal electrode that acts as the mask during back illumination of a photoresist layer followed by a conventional lift-off process step. On the other hand in the a-Lith approach, the surface energy of a patterned metal electrode is modified through the use of surface energy modifiers such as organic self-assembling monolayer (SAM). Following, a second metal is evaporated on the entire substrate. However, because of the present of the SAM, regions of metal-2 overlapping with metal-1 can easily be peeled off with the aid of an adhesive layer (e.g. sticky tape) leaving behind the two metal electrodes in close proximity to each other. Analysis of the resulting structures reveals that inter-electrode distances <20 nm can easily be achieved. The method was then used to develop innovative process protocols for the fabrication of functional self-aligned gate (SAG) transistor architectures. Best performing devices exhibited charge carrier mobility in the range of 0.5-1 cm2/Vs, high current on-off ratio (~104), negligible operating hysteresis and excellent switching speed. Using the same a-Lith process protocol, low-voltage organic ferroelectric tunnel junction memory devices were also developed by combining the metal-1/metal-2 nanogap electrodes with a ferroelectric copolymer deposited in-between them. Controllable ferroelectric tunnelling was observed enabling the devices’ conductivity to be programmed using low biases and hence been used as a non-volatile memory cell. The alternative and highly scalable patterning methods described in this thesis may one day play a significant role on how largearea electronics of the future would be manufactured.Open Acces

Low-temperature amorphous oxide semiconductors for thin-film transistors and memristors: physical insights and applications

While amorphous oxides semiconductors (AOS), namely InGaZnO (IGZO), have found market application in the display industry, their disruptive properties permit to envisage for more advanced concepts such as System-on-Panel (SoP) in which AOS devices could be used for addressing (and readout) of sensors and displays, for communication, and even for memory as oxide memristors are candidates for the next-generation memories. This work concerns the application of AOS for these applications considering the low thermal budgets (< 180 °C) required for flexible, low cost and alternative substrates. For maintaining low driving voltages, a sputtered multicomponent/multi-layered high-κ dielectric (Ta2O5+SiO2) was developed for low temperature IGZO TFTs which permitted high performance without sacrificing reliability and stability. Devices’ performance under temperature was investigated and the bias and temperature dependent mobility was modelled and included in TCAD simulation. Even for IGZO compositions yielding very high thermal activation, circuit topologies for counteracting both this and the bias stress effect were suggested. Channel length scaling of the devices was investigated, showing that operation for radio frequency identification (RFID) can be achieved without significant performance deterioration from short channel effects, which are attenuated by the high-κ dielectric, as is shown in TCAD simulation. The applicability of these devices in SoP is then exemplified by suggesting a large area flexible radiation sensing system with on-chip clock-generation, sensor matrix addressing and signal read-out, performed by the IGZO TFTs. Application for paper electronics was also shown, in which TCAD simulation was used to investigate on the unconventional floating gate structure. AOS memristors are also presented, with two distinct operation modes that could be envisaged for data storage or for synaptic applications. Employing typical TFT methodologies and materials, these are ease to integrate in oxide SoP architectures

Development of eco-friendly ZnO inks for paper-based printed electronics

In this work, we report the development of printable semiconducting inks compatible with screen-printing and paper technology and functional at room temperature without the need of post-deposition treatments. The developed eco-friendly inks are based on a dispersion of zinc oxide nanoparticles on a cellulose matrix. Several cellulose derivatives were used to design and engineer such inks looking for the best formulation, printing conditions and compatibility with cellulose-based substrates. The approach described here represents an innovative and versatile generation of semiconducting inks composed of some of the cheapest, renewable and highly abundant materials we can find on Earth, such as cellulose, able to be implemented as channel in printed transistors on paper. By using a cellulose-based ion gel as gate dielectric the printed ZnO transistors exhibit an Ion=of f ratio ranging from 103 to 105, sat values close to 9 cm2 V 1 s1 and gm of around 0.4 mS

Large-area flexible electronics based on low-temperature solution-processed oxide semiconductors

Due to their high charge carrier mobility, optical transparency and mechanical flexibility, thin-film transistors (TFTs) based on metal oxide semiconductors represent an emerging technology that offers the potential to revolutionise the next-generations of large-area electronics. This thesis focuses on the development of high-performance TFTs based on low-temperature, solution-processed metal oxide semiconductors that are compatible with inexpensive flexible plastic substrates. The first part of the dissertation describes an ultraviolet light assisted processing method suitable for room-temperature activation of ZnO nanoparticles and their application as semiconducting channels in TFTs. The impact of the semiconductor/dielectric interface on electrical performance is studied using different device configurations and dielectric surface-passivation methods. Furthermore, a nanocomposite concept is proposed in order to assist electron transport between different crystalline domains. Using this approach, TFTs with electron mobilities of ~3 cm2/Vs are demonstrated. The second part of this work explores a carbon-free, aqueous-based Zn-ammine complex route for the synthesis of polycrystalline ZnO thin-films at low temperature and their subsequent use in TFTs. Concurrently, the development of a complementary high-κ oxide dielectric system enables the demonstration of high-performance ZnO TFTs with electron mobilities >10 cm2/Vs and operation voltage down to ~1.2 V. This low-temperature aqueous chemistry is further explored using a facile n-type doping approach. Enhancement in electrical performance is attributed to the different crystallographic properties of the Al-doped ZnO layers. The final part of the thesis introduces a novel TFT concept that exploits the enhanced electron transport properties of low-dimensional polycrystalline quasi-superlattices (QSLs), consisting of sequentially spin-cast layers of In2O3, Ga2O3 and ZnO deposited at temperatures 40 cm2/Vs - an order of magnitude higher than devices based on single binary oxide layers. Based on temperature dependent electron transport and capacitance-voltage measurements, it is reasoned that the enhanced electrical performance arises from the presence of quasi two-dimensional electron gas-like systems formed at the carefully engineered oxide heterointerfaces buried within the QSLs.Open Acces

Design, Modeling and Analysis of Non-classical Field Effect Transistors

Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization

High-performance Zinc Oxide Thin-Film Transistors For Large Area Electronics

The increasing demand for high performance electronics that can be fabricated onto large area substrates employing low manufacturing cost techniques in recent years has fuelled the development of novel semiconductor materials such as organics and metal oxides, with tailored physical characteristics that are absent in their traditional inorganic counterparts such as silicon. Metal oxide semiconductors, in particular, are highly attractive for implementation into thin-film transistors because of their high charge carrier mobility, optical transparency, excellent chemical stability, mechanical stress tolerance and processing versatility. This thesis focuses on the development of high performance transistors based on zinc oxide (ZnO) semiconducting films grown by spray pyrolysis (SP), a low cost and highly scalable method that has never been used before for the manufacturing of oxide-based thin-film transistors. The physical properties of as-grown ZnO films have been studied using a range of techniques. Despite the simplicity of SP, as-fabricated transistors exhibit electrical characteristics comparable to those obtained from ZnO devices produced using highly sophisticated deposition processes. In particular, electron mobility up to 25 cm2/Vs has been achieved in transistors based on pristine ZnO films grown at 400 °C onto Si/SiO2 substrates utilising aluminium source-drain (S-D) electrodes. A strong dependence of the saturation mobility on the work function of S-D electrodes and the transistor channel length (L) has been established. Short channel transistors are found to exhibit improved performance as compared to long channel ones. This was attributed to grain boundary effects that tend to dominate charge transport in devices with L < 40 μm. High mobility, low operating voltage (<1.5 V) ZnO transistors have also been developed and characterised. This was achieved through the combination of SP, for the deposition of ZnO, and thermally stable solution-processed self-assembling monolayer gate dielectrics. Detailed study of the temperature dependence of the operating characteristics of ZnO transistors revealed a thermally activated electron transport process that was described by invoking the multiple trapping and release model. Importantly, ZnO transistors fabricated by SP are found to exhibit highly stable operating characteristics with a shelf lifetime of several months. The simple SPbased fabrication paradigm demonstrated in this thesis expands the possibilities for the development of advanced simple as well as multi-component oxide semiconductors far beyond those accessible by traditional deposition methods such as sputtering. Furthermore, it offers unprecedented processing scalability hence making it attractive for the manufacturing of future ubiquitous oxide electronics