Noisy Gradient Descent Bit-Flip Decoding for LDPC Codes

A modified Gradient Descent Bit Flipping (GDBF) algorithm is proposed for decoding Low Density Parity Check (LDPC) codes on the binary-input additive white Gaussian noise channel. The new algorithm, called Noisy GDBF (NGDBF), introduces a random perturbation into each symbol metric at each iteration. The noise perturbation allows the algorithm to escape from undesirable local maxima, resulting in improved performance. A combination of heuristic improvements to the algorithm are proposed and evaluated. When the proposed heuristics are applied, NGDBF performs better than any previously reported GDBF variant, and comes within 0.5 dB of the belief propagation algorithm for several tested codes. Unlike other previous GDBF algorithms that provide an escape from local maxima, the proposed algorithm uses only local, fully parallelizable operations and does not require computing a global objective function or a sort over symbol metrics, making it highly efficient in comparison. The proposed NGDBF algorithm requires channel state information which must be obtained from a signal to noise ratio (SNR) estimator. Architectural details are presented for implementing the NGDBF algorithm. Complexity analysis and optimizations are also discussed.Comment: 16 pages, 22 figures, 2 table

High performance binary LDPC-coded OFDM systems over indoor PLC channels

Power line communication (PLC) technology is actually among the most renowned technologies for home environments due to their low-cost installation opportunities. In this study, the bit error rate (BER) performances of binary low-density parity check (LDPC) coded orthogonal frequency-division multiplexing (OFDM) systems have been considered over indoor PLC channels. Performances comparison of diverse soft and hard decision LDPC decoder schemes such as Min-Sum (MS), weighted bit flipping (WBF), gradient descent bit-flip (GDBF), noisy gradient descent bit-flip (NGDBF) and its few variants including the single-bit NGDBF (S-NGDBF), multi-bit NGDBF (M-NGDBF) and smoothed-multi-bit NGDBF (SM-NGDBF) decoders were examined in the modeled network. To evaluate the BER performance analyses three different PLC channel scenarios were generated by using new and more realistic PLC channel model proposal were also employed. All of the simulations performed in Canete’s PLC channel model showed that remarkable performance improvement can be achieved by using short-length LDPC codes. Especially, the improvements are striking when the MS or SM-NGDBF decoding algorithms are employed on the receiver side

Low-Power 400-Gbps Soft-Decision LDPC FEC for Optical Transport Networks

We present forward error correction systems based on soft-decision low-density parity check (LDPC) codes for applications in 100–400-Gbps optical transport networks. These systems are based on the low-complexity “adaptive degeneration” decoding algorithm, which we introduce in this paper, along with randomly-structured LDPC codes with block lengths from 30 000 to 60 000 bits and overhead (OH) from 6.7% to 33%. We also construct a 3600-bit prototype LDPC code with 20% overhead, and experimentally show that it has no error floor above a bit error rate (BER) of 10−15 using a field-programmable gate array (FPGA)-based hardware emulator. The projected net coding gain at a BER of 10−15 ranges from 9.6 dB at 6.7% OH to 11.2 dB at 33% OH. We also present application-specific integrated circuit synthesis results for these decoders in 28 nm fully depleted silicon on insulator technology, which show that they are capable of 400-Gbps operation with energy consumption of under 3 pJ per information bit

A Practical Nonbinary Decoder for Low-Density Parity-Check Codes with Packet-Sized Symbols

This paper presents a practical decoder for regular low-density parity-check (LDPC) codes with flexible packet-sized symbols. The proposed hMP-VSD (Combined hard-decision message-passing with vector symbol decoding) is much less complex than the conventional VSD and has the same decoding performance. Regular LDPC codes with systematic encoding are selected for implementation. The channel is assumed to be the q-ary symmetric channel (q-SC). Different code lengths and column weights of LDPC codes are investigated. The results show that the codes with a column weight of 7 provide the best performance for hMP-VSD, while hMP works best with codes having a column weight of 5. With packet-sized symbols, even the rather short (60, 30) code structure has code lengths of 1,920 to 245,760 bits with symbol sizes of 32 to 4,096 bits. Both the decoder and its encoder were implemented on Raspberry-pi 4 model B boards and these results confirm that the computation time of hMP-VSD is 60% to 70% lower than that of VSD for pe in the range 0.05 to 0.1

Gradient-Descent Bit-Flipping Decoding Based on Tabu Search for LDPC Codes

This paper is concerned with bit-flipping algorithms for decoding low-density parity check codes. The gradient-descent bit flipping (GDBF) is known as a high-performance class of bitflipping algorithms; however, once GDBF becomes trapped at local optimal solutions, it cannot escape from them. Several algorithms, including noisy gradient-descent bit flipping (NGDBF), have been devised to overcome this drawback. For the same purpose, we develop a bit-flipping algorithm based on the tabu search, which is one of the most effective metaheuristics. The simulation results demonstrate that our algorithm achieved higher bit error rate performance than GDBF did. Moreover, our algorithm required a smaller number of iterations to find a good-quality solution than NGDBF did

A survey of FPGA-based LDPC decoders

Low-Density Parity Check (LDPC) error correction decoders have become popular in communications systems, as a benefit of their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into LDPC decoder designs that exploit the flexibility, the high processing speed and the parallelism of Field-Programmable Gate Array (FPGA) devices. FPGAs are ideal for design prototyping and for the manufacturing of small-production-run devices, where their in-system programmability makes them far more cost-effective than Application-Specific Integrated Circuits (ASICs). However, the FPGA-based LDPC decoder designs published in the open literature vary greatly in terms of design choices and performance criteria, making them a challenge to compare. This paper explores the key factors involved in FPGA-based LDPC decoder design and presents an extensive review of the current literature. In-depth comparisons are drawn amongst 140 published designs (both academic and industrial) and the associated performance trade-offs are characterised, discussed and illustrated. Seven key performance characteristics are described, namely their processing throughput, latency, hardware resource requirements, error correction capability, processing energy efficiency, bandwidth efficiency and flexibility. We offer recommendations that will facilitate fairer comparisons of future designs, as well as opportunities for improving the design of FPGA-based LDPC decoder