Can a second order bandpass sigma delta modulator achieve high signal-to-noise ratio for lowpass inputs

Institutively, second order SDMs usually achieve lower SNR than high order ones because high order loop filters can achieve better noise shaping characteristics. Moreover, the signal transfer function should be designed to have large values and the noise transfer function should be designed to have small values at the passband of loop filters in order to achieve good noise shaping characteristics, so SNR should be high if input signal bands match passbands of loop filters and low otherwise. Based on this argument, one may expect that SNR will be low when input signals have lowpass characteristics while loop filters have bandpass characteristics. However, since the above argument is based on the noise shaping theory which is formulated using a linear model, while quantizers in SDMs are nonlinear components, the linear model may not explain nonlinear system behaviors. In this letter, a counterexample is given to illustrate that a second order bandpass interpolative SDM may also give a very high SNR for lowpass inputs

Quantization Noise Shaping for Information Maximizing ADCs

ADCs sit at the interface of the analog and digital worlds and fundamentally determine what information is available in the digital domain for processing. This paper shows that a configurable ADC can be designed for signals with non constant information as a function of frequency such that within a fixed power budget the ADC maximizes the information in the converted signal by frequency shaping the quantization noise. Quantization noise shaping can be realized via loop filter design for a single channel delta sigma ADC and extended to common time and frequency interleaved multi channel structures. Results are presented for example wireline and wireless style channels.Comment: 4 pages, 6 figure

Multiple-Description Coding by Dithered Delta-Sigma Quantization

We address the connection between the multiple-description (MD) problem and Delta-Sigma quantization. The inherent redundancy due to oversampling in Delta-Sigma quantization, and the simple linear-additive noise model resulting from dithered lattice quantization, allow us to construct a symmetric and time-invariant MD coding scheme. We show that the use of a noise shaping filter makes it possible to trade off central distortion for side distortion. Asymptotically as the dimension of the lattice vector quantizer and order of the noise shaping filter approach infinity, the entropy rate of the dithered Delta-Sigma quantization scheme approaches the symmetric two-channel MD rate-distortion function for a memoryless Gaussian source and MSE fidelity criterion, at any side-to-central distortion ratio and any resolution. In the optimal scheme, the infinite-order noise shaping filter must be minimum phase and have a piece-wise flat power spectrum with a single jump discontinuity. An important advantage of the proposed design is that it is symmetric in rate and distortion by construction, so the coding rates of the descriptions are identical and there is therefore no need for source splitting.Comment: Revised, restructured, significantly shortened and minor typos has been fixed. Accepted for publication in the IEEE Transactions on Information Theor

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

NOISE SHAPING IN SAR ADC

The successive approximation register (SAR) analog-to-digital converter (ADC) is currently the most popular type of ADC architecture, owing to its power efficiency. They are also used in multichannel systems, where power efficiency is of high importance because of the large number of simultaneously working channels. However, the SAR ADC architecture is not the most area efficient. In SAR ADCs, the binary weighted capacitive digital-to-analog converter (DAC) is used, which means that one additional bit of resolution costs double the increase of area. Oversampling and noise shaping are methods that allow an increase in resolution without an increase of area. In this paper we present the new SAR ADC architectures with a noise shaping. A first-order noise transfer function (NTF) with zero located nearly at one can be achieved. We propose two modifications of the architecture: with zero-only NTF and with the NTF with additional pole. The additional pole theoretically increases the efficiency of noise shaping to further 3 dB. The architectures were applied to the design of SAR ADCs in a 65 nm complementary metal-oxide semiconductor (CMOS) with OSR equal to 10. A 6-bit capacitive DAC was used. The proposed  architectures  provide nearly 4 additional bits in ENOB. The equalent input bandwitdth is equal to 200 kHz with the sampling rate equal to 4 MS/s

Analysis of VCO based noise shaping ADCs linearized by PWM modulation

Nonlinearity is one of the main problems associated with VCO based noise shaping ADCs. Their open loop architecture does not permit correction of the nonlinear voltage to frequency response of the VCO by feedback. Recently, linearization of a VCO ADC by Pulse Width Modulation (PWM) precoding has been proposed. Here, the input signal is encoded by a PWM modulator to drive the VCO with a 2-level signal, thus eliminating the nonlinearity of the VCO. This paper analyzes the remaining inherent distortion in such modulators which originates from subsampling the PWM sidebands