The successive approximation register (SAR) analog-to-digital converter (ADC) is currently the most popular type of ADC architecture, owing to its power efficiency. They are also used in multichannel systems, where power efficiency is of high importance because of the large number of simultaneously working channels. However, the SAR ADC architecture is not the most area efficient. In SAR ADCs, the binary weighted capacitive digital-to-analog converter (DAC) is used, which means that one additional bit of resolution costs double the increase of area. Oversampling and noise shaping are methods that allow an increase in resolution without an increase of area. In this paper we present the new SAR ADC architectures with a noise shaping. A first-order noise transfer function (NTF) with zero located nearly at one can be achieved. We propose two modifications of the architecture: with zero-only NTF and with the NTF with additional pole. The additional pole theoretically increases the efficiency of noise shaping to further 3 dB. The architectures were applied to the design of SAR ADCs in a 65 nm complementary metal-oxide semiconductor (CMOS) with OSR equal to 10. A 6-bit capacitive DAC was used. The proposed architectures provide nearly 4 additional bits in ENOB. The equalent input bandwitdth is equal to 200 kHz with the sampling rate equal to 4 MS/s
