Study of Adjustable Gains for Control of Oscillation Frequency and Oscillation Condition in 3R-2C Oscillator

An idea of adjustable gain in order to obtain controllable features is very useful for design of tuneable oscillators. Several active elements with adjustable properties (current and voltage gain) are discussed in this paper. Three modified oscillator conceptions that are quite simple, directly electronically adjustable, providing independent control of oscillation condition and frequency were designed. Positive and negative aspects of presented method of control are discussed. Expected assumptions of adjustability are verified experimentally on one of the presented solution

Deriving (MO)(I)CCCII Based Second-order Sinusoidal Oscillators with Non-interactive Tuning Laws using State Variable Method

The paper discusses systematic realization of second-order sinusoidal oscillators using multiple-output second-generation current controlled conveyor (MO-CCCII) and/or its inverting equivalent, namely the multiple-output inverting second-generation current controlled conveyor (MO-ICCCII) by state variable method. State variable method is a powerful technique and has been used extensively in the past to realize active RC oscillators using a variety of active building blocks (ABB). In this work, a noninteractive relationship between the condition of oscillation (CO) and the frequency of oscillation (FO) has been chosen priori and then state variable method is applied to derive the oscillators with grounded capacitors. All the resulting oscillator circuits, eight of them, are “resistor-less”, employ grounded capacitors and do not use more than three (MO)(I)CCCIIs. PSPICE simulation results of a possible CMOS implementation of the oscillators using 0:35μm TSMC CMOS technology parameters have validated their workability

Log-domain All-pass Filter-based Multiphase Sinusoidal Oscillators

Log-domain current-mode multiphase sinusoidal oscillators based on all-pass filters are presented in this paper. The first-order differential equation is used for obtaining inverting and non-inverting all-pass filters. The proposed oscillators are realized by all-pass filters which can be electronically tuned their natural frequency and stage gain by adjusting the bias currents. Each all pass filter contains 10 NPN transistors and a grounded capacitor. The validated BJT model which used in SPICE simulation operated by a single power supply as low as 2.5 V. The frequency of oscillation can be controlled over four decades. The total harmonic distortions of these MSO at frequency 56.67 MHz and 54.44 MHz, obtained around 0.52% and 0.75%, respectively. The proposed circuits enable fully integrated in telecommunication systems and also suit to high-frequency applications. Nonideality studies and PSpice simulation results are included to confirm the theory

Circuits for Analog Signal Processing Employing Unconventional Active Elements

Disertační práce se zabývá zaváděním nových struktur moderních aktivních prvků pracujících v napěťovém, proudovém a smíšeném režimu. Funkčnost a chování těchto prvků byly ověřeny prostřednictvím SPICE simulací. V této práci je zahrnuta řada simulací, které dokazují přesnost a dobré vlastnosti těchto prvků, přičemž velký důraz byl kladen na to, aby tyto prvky byly schopny pracovat při nízkém napájecím napětí, jelikož poptávka po přenosných elektronických zařízeních a implantabilních zdravotnických přístrojích stále roste. Tyto přístroje jsou napájeny bateriemi a k tomu, aby byla prodloužena jejich životnost, trend navrhování analogových obvodů směřuje k stále většímu snižování spotřeby a napájecího napětí. Hlavním přínosem této práce je návrh nových CMOS struktur: CCII (Current Conveyor Second Generation) na základě BD (Bulk Driven), FG (Floating Gate) a QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) na základě FG, transkonduktor na základě nové techniky BD_QFG (Bulk Driven_Quasi Floating Gate), CCCDBA (Current Controlled Current Differencing Buffered Amplifier) na základě GD (Gate Driven), VDBA (Voltage Differencing Buffered Amplifier) na základě GD a DBeTA (Differential_Input Buffered and External Transconductance Amplifier) na základě BD. Dále je uvedeno několik zajímavých aplikací užívajících výše jmenované prvky. Získané výsledky simulací odpovídají teoretickým předpokladům.The dissertation thesis deals with implementing new structures of modern active elements working in voltage_, current_, and mixed mode. The functionality and behavior of these elements have been verified by SPICE simulation. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of those elements. However, a big attention to implement active elements by utilizing LV LP (Low Voltage Low Power) techniques is given in this thesis. This attention came from the fact that growing demand of portable electronic equipments and implantable medical devices are pushing the development towards LV LP integrated circuits because of their influence on batteries lifetime. More specifically, the main contribution of this thesis is to implement new CMOS structures of: CCII (Current Conveyor Second Generation) based on BD (Bulk Driven), FG (Floating Gate) and QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) based on FG; Transconductor based on new technique of BD_QFG (Bulk Driven_Quasi Floating Gate); CCCDBA (Current Controlled Current Differencing Buffered Amplifier) based on conventional GD (Gate Driven); VDBA (Voltage Differencing Buffered Amplifier) based on GD. Moreover, defining new active element i.e. DBeTA (Differential_Input Buffered and External Transconductance Amplifier) based on BD is also one of the main contributions of this thesis. To confirm the workability and attractive properties of the proposed circuits many applications were exhibited. The given results agree well with the theoretical anticipation.

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Current Gain Controlled CCTA and its Application in Quadrature Oscillator and Direct Frequency Modulator

A modified conception of adjustable current conveyor transconductance amplifier (CCTA) and its interesting application in simple quadrature oscillator expandable for direct frequency modulation purposes, employing only four grounded passive elements is presented in this paper. It is quite simple solution for modern communication subsystem components. An electronic adjusting of the oscillation frequency is easily possible and control of condition of the oscillation is realized via only one grounded resistor. The characteristic equation, condition of oscillation and major parasitic influences of real active part are discussed. The verification includes PSpice simulation and measurement with the CCTA block formed by commercially available active elements

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Epitaxial designs for maximizing efficiency in resonant tunnelling diode based terahertz emitters

We discuss the modelling of high current density InGaAs/AlAs/InP resonant tunneling diodes to maximize their efficiency as THz emitters. A figure of merit which contributes to the wall plug efficiency, the intrinsic resonator efficiency, is used for the development of epitaxial designs. With the contribution of key parameters identified, we analyze the limitations of accumulated stress to assess the manufacturability of such designs. Optimal epitaxial designs are revealed, utilizing thin barriers, with a wide and shallow quantum well that satisfies the strained layer epitaxy constraint. We then assess the advantages to epitaxial perfection and electrical characteristics provided by devices with a narrow InAs sub-well inside a lattice-matched InGaAs alloy. These new structures will assist in the realization of the next-generation submillimeter emitters