Closed form metrics to accurately model the response in general arbitrarily-coupled RC trees.

Closed form expressions are presented for the first and second moment of the impulse response for arbitrarily-coupled RC trees with multiple drivers, and used to generate accurate second order estimations of the transfer function from any driver to the receiver. The superposition of the waveforms for all switching events allows precise delay and noise calculations for systems of coupled interconnects with different aggressor arrival times, with a minimum of computational complexity

Delay Extraction Based Equivalent Elmore Model For RLC On-Chip Interconnects

As feature sizes for VLSI technology is shrinking, associated with higher operating frequency, signal integrity analysis of on-chip interconnects has become a real challenge for circuit designers. For this purpose, computer-aided-design (CAD) tools are necessary to simulate signal propagation of on-chip interconnects which has been an active area for research. Although SPICE models exist which can accurately predict signal degradation of interconnects, they are computationally expensive. As a result, more effective and analytic models for interconnects are required to capture the response at the output of high speed VLSI circuits. This thesis contributes to the development of efficient and closed form solution models for signal integrity analysis of on-chip interconnects. The proposed model uses a delay extraction algorithm to improve the accuracy of two-pole Elmore based models used in the analysis of on-chip distributed RLC interconnects. In the proposed scheme, the time of fight signal delay is extracted without increasing the number of poles or affecting the stability of the transfer function. This algorithm is used for both unit step and ramp inputs. From the delay rational approximation of the transfer function, analytic fitted expressions are obtained for the 50% delay and rise time for unit step input. The proposed algorithm is tested on point to point interconnections and tree structure networks. Numerical examples illustrate improved 50% delay and rise time estimates when compared to traditional Elmore based two-pole models

EARLY PERFORMANCE PREDICTION METHODOLOGY FOR MANY-CORES ON CHIP BASED APPLICATIONS

Modern high performance computing applications such as personal computing, gaming, numerical simulations require application-specific integrated circuits (ASICs) that comprises of many cores. Performance for these applications depends mainly on latency of interconnects which transfer data between cores that implement applications by distributing tasks. Time-to-market is a critical consideration while designing ASICs for these applications. Therefore, to reduce design cycle time, predicting system performance accurately at an early stage of design is essential. With process technology in nanometer era, physical phenomena such as crosstalk, reflection on the propagating signal have a direct impact on performance. Incorporating these effects provides a better performance estimate at an early stage. This work presents a methodology for better performance prediction at an early stage of design, achieved by mapping system specification to a circuit-level netlist description. At system-level, to simplify description and for efficient simulation, SystemVerilog descriptions are employed. For modeling system performance at this abstraction, queueing theory based bounded queue models are applied. At the circuit level, behavioral Input/Output Buffer Information Specification (IBIS) models can be used for analyzing effects of these physical phenomena on on-chip signal integrity and hence performance. For behavioral circuit-level performance simulation with IBIS models, a netlist must be described consisting of interacting cores and a communication link. Two new netlists, IBIS-ISS and IBIS-AMI-ISS are introduced for this purpose. The cores are represented by a macromodel automatically generated by a developed tool from IBIS models. The generated IBIS models are employed in the new netlists. Early performance prediction methodology maps a system specification to an instance of these netlists to provide a better performance estimate at an early stage of design. The methodology is scalable in nanometer process technology and can be reused in different designs

Analytic Delay Model of RLC Interconnects using Numerical Inversion of the Laplace Transform

Signal integrity analysis for on-chip interconnect becomes increasingly important in high-speed designs. SPICE, a conventional circuit simulator, can provide accurate prediction for interconnects, however, using SPICE is extremely computationally expensive. On the other hand, explicit moment matching technique can produce unstable poles for highly accurate approximations and implicit moment matching technique can obtain more accurate approximations at the expense of computational complexity. This thesis presents an analytic model to efficiently estimate the signal delays of RLC on-chip interconnects. It uses the numerical inversion of Laplace transform (NILT) to obtain time function, suitable for transient analysis. Since the integration formula of the NILT is numerically stable for higher order approximations, the developed algorithm provides a mechanism to increase the accuracy for delay estimation. Numerical examples are implemented and compared with HSPICE, two-pole model and Passive Reduced-Order Interconnect Macromodeling Algorithm (PRIMA) to illustrate the efficiency and validity of the proposed work

HIGH PERFORMANCE CLOCK DISTRIBUTION FOR HIGH-SPEED VLSI SYSTEMS

Tohoku University堀口 進課

Transient simulation of complex electronic circuits and systems operating at ultra high frequencies

The electronics industry worldwide faces increasingly difficult challenges in a bid to produce ultra-fast, reliable and inexpensive electronic devices. Electronic manufacturers rely on the Electronic Design Automation (EDA) industry to produce consistent Computer A id e d Design (CAD) simulation tools that w ill enable the design of new high-performance integrated circuits (IC), the key component of a modem electronic device. However, the continuing trend towards increasing operational frequencies and shrinking device sizes raises the question of the capability of existing circuit simulators to accurately and efficiently estimate circuit behaviour. The principle objective of this thesis is to advance the state-of-art in the transient simulation of complex electronic circuits and systems operating at ultra high frequencies. Given a set of excitations and initial conditions, the research problem involves the determination of the transient response o f a high-frequency complex electronic system consisting of linear (interconnects) and non-linear (discrete elements) parts with greatly improved efficien cy compared to existing methods and with the potential for very high accuracy in a way that permits an effective trade-off between accuracy and computational complexity. High-frequency interconnect effects are a major cause of the signal degradation encountered b y a signal propagating through linear interconnect networks in the modem IC. Therefore, the development of an interconnect model that can accurately and efficiently take into account frequency-dependent parameters of modem non-uniform interconnect is of paramount importance for state-of-art circuit simulators. Analytical models and models based on a set of tabulated data are investigated in this thesis. Two novel, h igh ly accurate and efficient interconnect simulation techniques are developed. These techniques combine model order reduction methods with either an analytical resonant model or an interconnect model generated from frequency-dependent sparameters derived from measurements or rigorous full-wave simulation. The latter part o f the thesis is concerned with envelope simulation. The complex mixture of profoundly different analog/digital parts in a modern IC gives rise to multitime signals, where a fast changing signal arising from the digital section is modulated by a slower-changing envelope signal related to the analog part. A transient analysis of such a circuit is in general very time-consuming. Therefore, specialised methods that take into account the multi-time nature o f the signal are required. To address this issue, a novel envelope simulation technique is developed. This technique combines a wavelet-based collocation method with a multi-time approach to result in a novel simulation technique that enables the desired trade-off between the required accuracy and computational efficiency in a simple and intuitive way. Furthermore, this new technique has the potential to greatly reduce the overall design cycle

Custom Integrated Circuits

Contains table of contents for Part III, table of contents for Section 1 and reports on eleven research projects.IBM CorporationMIT School of EngineeringNational Science Foundation Grant MIP 94-23221Defense Advanced Research Projects Agency/U.S. Army Intelligence Center Contract DABT63-94-C-0053Mitsubishi CorporationNational Science Foundation Young Investigator Award Fellowship MIP 92-58376Joint Industry Program on Offshore Structure AnalysisAnalog DevicesDefense Advanced Research Projects AgencyCadence Design SystemsMAFET ConsortiumConsortium for Superconducting ElectronicsNational Defense Science and Engineering Graduate FellowshipDigital Equipment CorporationMIT Lincoln LaboratorySemiconductor Research CorporationMultiuniversity Research IntiativeNational Science Foundatio

Signaling in 3-D integrated circuits, benefits and challenges

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed

Investigation of Interconnect and Device Designs for Emerging Post-MOSFET and Beyond Silicon Technologies

Title from PDF of title page viewed May 31, 2017Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 94-108)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2016The integrated circuit industry has been pursuing Moore’s curve down to deep nanoscale dimensions that would lead to the anticipated delivery of 100 billion transistors on a 300 mm² die operating below 1V supply in the next 5-10 years. However, the grand challenge is to reliably and efficiently take the full advantage of the unprecedented computing power offered by the billions of nanoscale transistors on a single chip. To mitigate this challenge, the limitations of both the interconnecting wires and semiconductor devices in integrated circuits have to be addressed. At the interconnect level, the major challenge in current high density integrated circuit is the electromagnetic and electrostatic impacts in the signal carrying lines. Addressing these problems require better analysis of interconnect resistance, inductance, and capacitance. Therefore, this dissertation has proposed a new delay model and analyzed the time-domain output response of complex poles, real poles, and double poles for resistance-inductance capacitance interconnect network based on a second order approximate transfer function. Both analytical models and simulation results show that the real poles model is much faster than the complex poles model, and achieves significantly higher accuracy in order to characterize the overshoot and undershoot of the output responses. On the other hand, the semiconductor industry is anticipating that within a decade silicon devices will be unable to meet the demands at nanoscale due to dimension and material scaling. Recently, molybdenum disulfide (MoS₂) has emerged as a new super material to replace silicon in future semiconductor devices. Besides, conventional field effect transistor technology is also reaching its thermodynamic limit. Breaking this thermal and physical limit requires adoption of new devices based on tunneling mechanism. Keeping the above mentioned trends, this dissertation also proposed a multilayer MoS₂ channel-based tunneling transistor and identifies the fundamental parameters and design specifications that need to be optimized in order to achieve higher ON-currents. A simple analytical model of the proposed device is derived by solving the time-independent Schrodinger equation. It is analytically proven that the proposed device can offer an ON-current of 80 A/m, a subthreshold swing (S) of 9.12 mV/decade, and a / ratio of 10¹².Introduction -- Previous models on interconnect designs -- Proposed delay model for interconnect design -- Investigation of tunneling for field effect transistor -- Study of molybdenum disulfide for FET applications -- Proposed molybdenum disulfide based tunnel transistor -- Conclusion -- Appendix A. Derivation of time delay model -- Appendix B. Derivation of tunneling current model Appendix C. Derivation of subthreshold swing mode

Integrated Circuits Parasitic Capacitance Extraction Using Machine Learning and its Application to Layout Optimization

The impact of parasitic elements on the overall circuit performance keeps increasing from one technology generation to the next. In advanced process nodes, the parasitic effects dominate the overall circuit performance. As a result, the accuracy requirements of parasitic extraction processes significantly increased, especially for parasitic capacitance extraction. Existing parasitic capacitance extraction tools face many challenges to cope with such new accuracy requirements that are set by semiconductor foundries (\u3c 5% error). Although field-solver methods can meet such requirements, they are very slow and have a limited capacity. The other alternative is the rule-based parasitic capacitance extraction methods, which are faster and have a high capacity; however, they cannot consistently provide good accuracy as they use a pre-characterized library of capacitance formulas that cover a limited number of layout patterns. On the other hand, the new parasitic extraction accuracy requirements also added more challenges on existing parasitic-aware routing optimization methods, where simplified parasitic models are used to optimize layouts. This dissertation provides new solutions for interconnect parasitic capacitance extraction and parasitic-aware routing optimization methodologies in order to cope with the new accuracy requirements of advanced process nodes as follows. First, machine learning compact models are developed in rule-based extractors to predict parasitic capacitances of cross-section layout patterns efficiently. The developed models mitigate the problems of the pre-characterized library approach, where each compact model is designed to extract parasitic capacitances of cross-sections of arbitrary distributed metal polygons that belong to a specific set of metal layers (i.e., layer combination) efficiently. Therefore, the number of covered layout patterns significantly increased. Second, machine learning compact models are developed to predict parasitic capacitances of middle-end-of-line (MEOL) layers around FINFETs and MOSFETs. Each compact model extracts parasitic capacitances of 3D MEOL patterns of a specific device type regardless of its metal polygons distribution. Therefore, the developed MEOL models can replace field-solvers in extracting MEOL patterns. Third, a novel accuracy-based hybrid parasitic capacitance extraction method is developed. The proposed hybrid flow divides a layout into windows and extracts the parasitic capacitances of each window using one of three parasitic capacitance extraction methods that include: 1) rule-based; 2) novel deep-neural-networks-based; and 3) field-solver methods. This hybrid methodology uses neural-networks classifiers to determine an appropriate extraction method for each window. Moreover, as an intermediate parasitic capacitance extraction method between rule-based and field-solver methods, a novel deep-neural-networks-based extraction method is developed. This intermediate level of accuracy and speed is needed since using only rule-based and field-solver methods (for hybrid extraction) results in using field-solver most of the time for any required high accuracy extraction. Eventually, a parasitic-aware layout routing optimization and analysis methodology is implemented based on an incremental parasitic extraction and a fast optimization methodology. Unlike existing flows that do not provide a mechanism to analyze the impact of modifying layout geometries on a circuit performance, the proposed methodology provides novel sensitivity circuit models to analyze the integrity of signals in layout routes. Such circuit models are based on an accurate matrix circuit representation, a cost function, and an accurate parasitic sensitivity extraction. The circuit models identify critical parasitic elements along with the corresponding layout geometries in a certain route, where they measure the sensitivity of a route’s performance to corresponding layout geometries very fast. Moreover, the proposed methodology uses a nonlinear programming technique to optimize problematic routes with pre-determined degrees of freedom using the proposed circuit models. Furthermore, it uses a novel incremental parasitic extraction method to extract parasitic elements of modified geometries efficiently, where the incremental extraction is used as a part of the routing optimization process to improve the optimization runtime and increase the optimization accuracy