New Resistorless and Electronically Tunable Realization of Dual-Output VM All-Pass Filter Using VDIBA

In this paper, a new active element called voltage differencing inverting buffered amplifier (VDIBA) is presented. Using single VDIBA and a capacitor, a new resistorless voltage-mode (VM) first-order all-pass filter (APF) is proposed, which provides both inverting and non-inverting outputs at the same configuration simultaneously. The pole frequency of the filter can be electronically controlled by means of bias current of the internal transconductance. No component-matching conditions are required and it has low sensitivity. In addition, the parasitic and loading effects are also investigated. By connecting two newly introduced APFs in open loop a novel second-order APF is proposed. As another application, the proposed VM APF is connected in cascade to a lossy integrator in a closed loop to design a four-phase quadrature oscillator. The theoretical results are verified by SPICE simulations using TSMC 0.18 um level-7 CMOS process parameters with +-0.9 V supply voltages. Moreover, the behavior of the proposed VM APF was also experimentally measured using commercially available integrated circuit OPA860 by Texas Instruments.In this paper, a new active element called voltage differencing inverting buffered amplifier (VDIBA) is presented. Using single VDIBA and a capacitor, a new resistorless voltage-mode (VM) first-order all-pass filter (APF) is proposed, which provides both inverting and non-inverting outputs at the same configuration simultaneously. The pole frequency of the filter can be electronically controlled by means of bias current of the internal transconductance. No component-matching conditions are required and it has low sensitivity. In addition, the parasitic and loading effects are also investigated. By connecting two newly introduced APFs in open loop a novel second-order APF is proposed. As another application, the proposed VM APF is connected in cascade to a lossy integrator in a closed loop to design a four-phase quadrature oscillator. The theoretical results are verified by SPICE simulations using TSMC 0.18 um level-7 CMOS process parameters with +-0.9 V supply voltages. Moreover, the behavior of the proposed VM APF was also experimentally measured using commercially available integrated circuit OPA860 by Texas Instruments

Realization of analog signal processing modules using carbon nanotube field effect transistors

This thesis presents the realization and performance analysis of several carbon nanotube field effect transistor (CNTFET) based analog signal processing (ASP) modules. CNTFET is predicted as a possible successor to conventional silicon complementary metal oxide semiconductor (CMOS), which has reached its scaling limits. The CMOS based ASP modules face significant challenges at deep nanoscale, resulting in severe performance degradations due to short channel effects. The main goal of this work is to realize CNTFET active building blocks (ABBs), and then to utilize these ABBs for realization of low-voltage, low-power, and high-frequency ASP modules. The proposed ABBs have low power dissipation, reduced parasitic components, and minimum number of CNTFETs. The proposed modules are active inductor (AI), first-order phase shifter, and second-order phase shifter. This research proposes a new CNTFET based grounded AI (GAI) circuit with high self-resonance frequency (SRF), wide tunable inductance range, and high quality factor. Simulation results demonstrate that the GAI offers tunable inductance from 4.4 nH to 287.4 nH with a maximum SRF of 101 GHz. It consumes very low power dissipation of 0.337 mW. In comparison to high performance available GAI circuits, the proposed GAI shows 34% reduction in power dissipation and nine times higher SRF. A highfrequency low-noise amplifier (LNA) circuit is also designed by utilizing the proposed GAI to showcase its application. The simulation result shows high frequency bandwidth of 17.5 GHz to 57 GHz, 15.9 dB maximum voltage gain, better than -10 dB input matching, and less than 3 dB noise figure. This research also proposes a compact wideband first-order phase shifter (FOPS) and active-only FOPS (AOFOPS). Simulation results demonstrate the FOPS has a tunable pole frequency range between 1.913 GHz and 40.2 GHz, input and output voltage noises of 4.402 nV/VHz and 4.414 nV/VH z respectively, and power dissipation of 0.4862 mW. The AOFOPS circuit also offers a wide tunable range of pole frequency between 34.2 GHz to 56.4 GHz with input noise and output noise of 6.822 nV/VHz and 6.761 nV/VHz respectively, and power dissipation of only 0.0338 mW. The AOFOPS dissipates 12.40 times less power in comparison to state-of-art FOPS circuits. This work also proposes active-only second-order phase shifter. The proposed circuit provides a tunable pole frequency between 16.2 GHz to 42.5 GHz, with input and output noises of 21.698 nV/VHz and 21.593 nV/VHz respectively, while consuming 0.2256 mW power. All circuit performances are verified through HSPICE simulation by utilizing the Stanford CNTFET model at 16 nm technology node with supply voltage of 0.7 V

Mixed-Mode Third-Order Quadrature Oscillator Based on Single MCCFTA

This paper presents a new mixed-mode third-order quadrature oscillator based on new modified current-controlled current follower transconductance amplifier (MCCFTA). The proposed circuit employs one MCCFTA as active element and three grounded capacitors as passive component which is highly suitable for integrated circuit implementation. The condition and frequency of oscillations can be controlled orthogonally and electronically by adjusting the bias currents of the active device. The circuit provides four quadrature current outputs and two quadrature voltage outputs into one single topology, which can be classified as mixed-mode oscillator. In addition, four quadrature current output terminals possess high-impedance level which can be directly connected to next stage without additional buffer circuits. The performance of the proposed structure has been verified through PSPICE simulators using 0.25 µm CMOS process from TSMC and experimental results are also investigated