Using Simple Neural Networks to Correct Errors in Optical Data Transmission.

We have demonstrated the applicability of neural-network-based systems to the problem of reducing the effects of signal distortion, and shown that such a system has the potential to reduce the bit-error-rate in the digitized version of the analogue electrical signal derived from an optical data stream by a substantial margin over existing techniques

Better branch prediction through prophet/critic hybrids

The prophet/critic hybrid conditional branch predictor has two component predictors. The prophet uses a branch's history to predict its direction. We call this prediction and the ones for branches following it the branch future. The critic uses the branch's history and future to critique the prophet's prediction. The hybrid combines the prophet's prediction with the critique, either agrees or disagree, forming the branch's overall prediction. Results shows these hybrids can reduce mispredicts by 39 percent and improve processor performance by 7.8 percent.Peer ReviewedPostprint (published version

Learning representations for binary-classification without backpropagation

The family of feedback alignment (FA) algorithms aims to provide a more biologically motivated alternative to backpropagation (BP), by substituting the computations that are unrealistic to be implemented in physical brains. While FA algorithms have been shown to work well in practice, there is a lack of rigorous theory proofing their learning capabilities. Here we introduce the first feedback alignment algorithm with provable learning guarantees. In contrast to existing work, we do not require any assumption about the size or depth of the network except that it has a single output neuron, i.e., such as for binary classification tasks. We show that our FA algorithm can deliver its theoretical promises in practice, surpassing the learning performance of existing FA methods and matching backpropagation in binary classification tasks. Finally, we demonstrate the limits of our FA variant when the number of output neurons grows beyond a certain quantity

A Hybrid Neural Based Dynamic Branch Prediction Unit

Modern high performance processor architectures have come to depend upon highly pipelined operation in order to achieve improvements in operating speed. As a result, the cost associated with flushing the pipeline and refilling it when a branch instruction is mis-predicted can significantly impact processor performance. Many schemes, from the extremely simple to the highly complex, have been proposed to improve branch prediction accuracy. Conventional two-level branch predictors predict the outcome of a branch either based on the( local branch history) information, comprising the previous outcomes of a single branch (intra-branch correlation), or based on the (global branch history) information, comprising the previous outcomes of all branches (inter-branch correlation). The misprediction rates for these predictors are very high when they predict branch instructions with hybrid correlations. In this paper we suggest a hybrid perceptron based predictor which employs up to 31-bits of both local and global branch history information to minimize the misprediction rates. The software written for simulation and testing shows that the suggested hybrid predictor achieves a high accuracy. Our results shows that the best response of the predictor is obtained on history length of 16- bits

The Impact of Java Applications at Microarchitectural Level from Branch Prediction Perspective

The portability, the object-oriented and distributed programming models, multithreading support and automatic garbage collection are features that make Java very attractive for application developers. The main goal of this paper consists in pointing out the impact of Java applications at microarchitectural level from two perspectives: unbiased branches and indirect jumps/calls, such branches limiting the ceiling of dynamic branch prediction and causing significant performance degradation. Therefore, accurately predicting this kind of branches remains an open problem. The simulation part of the paper mainly refers to determining the context length influence on the percentage of unbiased branches from Java applications, the prediction accuracy and the usage degree obtained using a Fast Path-Based Perceptron predictor. We realize a comparison with C/C++ application behavior from unbiased branches perspective. We also analyze some Java testing programs, built using design patterns or including inheritance, polymorphism, backtracking and recursivity, in order to determine the features of indirect branches, the arity of each indirect jump and the prediction accuracy using the Target Cache predictor

Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction

Long-latency load requests continue to limit the performance of high-performance processors. To increase the latency tolerance of a processor, architects have primarily relied on two key techniques: sophisticated data prefetchers and large on-chip caches. In this work, we show that: 1) even a sophisticated state-of-the-art prefetcher can only predict half of the off-chip load requests on average across a wide range of workloads, and 2) due to the increasing size and complexity of on-chip caches, a large fraction of the latency of an off-chip load request is spent accessing the on-chip cache hierarchy. The goal of this work is to accelerate off-chip load requests by removing the on-chip cache access latency from their critical path. To this end, we propose a new technique called Hermes, whose key idea is to: 1) accurately predict which load requests might go off-chip, and 2) speculatively fetch the data required by the predicted off-chip loads directly from the main memory, while also concurrently accessing the cache hierarchy for such loads. To enable Hermes, we develop a new lightweight, perceptron-based off-chip load prediction technique that learns to identify off-chip load requests using multiple program features (e.g., sequence of program counters). For every load request, the predictor observes a set of program features to predict whether or not the load would go off-chip. If the load is predicted to go off-chip, Hermes issues a speculative request directly to the memory controller once the load's physical address is generated. If the prediction is correct, the load eventually misses the cache hierarchy and waits for the ongoing speculative request to finish, thus hiding the on-chip cache hierarchy access latency from the critical path of the off-chip load. Our evaluation shows that Hermes significantly improves performance of a state-of-the-art baseline. We open-source Hermes.Comment: To appear in 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 202

Combinaciones Léxicas en el Inglés de la Tecnología.

A part of corpus-based research has centered on the exploration of lexical phrases (Sinclair 1991; Gledhill 2000a, 2000b; Stubbs 2002) and has presented language as a series of choices determined by the context in which it is employed. Native speakers use recurrent lexico-grammatical patterns when communicating in particular registers. This is especially relevant in scientific academic discourse, where the conventions of genres are interwoven with their linguistic realisations. Following Sinclair (1991: 170), a collocation is defined as “the occurrence of two or more words within a spot of space of each other in a text”. The restrictive character of collocations is basically determined by their repetitive use, which makes word combinations more arbitrary than predictable. This is particularly evident when we try to translate these combinations into other languages. Benson et al. (1986) suggest that collocations are halfway between fixed expressions and free combinations of words. They are co-occurrent groups of words that present a certain degree of stability, although they are not completely lexicalised. Collocations can be situated along a scale or continuum limited by free combinations of words at one end and fixed expressions at the other. The study of collocational patterns has direct pedagogical applications. Learners are not usually taught collocations explicitly. However, we believe that the acquisition of phraseological competence is necessary for effective and precise communication. In the area of English language teaching, the works of Howarth (1993, 1996), Oakey (2002) and Tribble (1990, 2002) point out the importance of collocations in academic writing. Other studies propose the teaching of grammar prioritising the behaviour of individual lexical units (or pattern grammar), i.e. taking account of the lexical patterns of a given register (cf. Hunston 1995, 2002). The aim of this paper is to explore the collocational patterns of three semitechnical and specialised words used in a corpus of 54 engineering research articles in the fields of computing, robotics and nanotechnology: robot, performance and lattice. The analysis shows that, although these words can be found in general English, their collocates contribute to restrict and precise their meaning in a specialised corpus. Making learners aware of these patterns should arouse their consciousness of the use of language in specialized contexts and help them to improve their academic writing as regards accuracy and fluency