Performance evaluation of data-driven techniques for the softwarized and agnostic management of an N×N photonic switch

The emerging Software Defined Networking (SDN) paradigm paves the way for flexible and automatized management at each layer. The SDN-enabled optical network requires each network element’s software abstraction to enable complete control by the centralized network controller. Nowadays, silicon photonics due to its low energy consumption, low latency, and small footprint is a promising technology for implementing photonic switching topologies, enabling transparent lightpath routing in re-configurable add-drop multiplexers. To this aim, a model for the complete management of photonic switching systems’ control states is fundamental for network control. Typically, photonics-based switches are structured by exploiting the modern technology of Photonic Integrated Circuit (PIC) that enables complex elementary cell structures to be driven individually. Thus PIC switches’ control states are combinations of a large set of elementary controls, and their definition is a challenging task. In this scenario, we propose the use of several data-driven techniques based on Machine Learning (ML) to model the control states of a PIC N×N photonic switch in a completely blind manner. The proposed ML-based techniques are trained and tested in a completely topological and technological agnostic way, and we envision their application in a real-time control plane. The proposed techniques’ scalability and accuracy are validated by considering three different switching topologies: the Honey-Comb Rearrangeable Optical Switch (HCROS), Spanke-Beneš, and the Beneš network. Excellent results in terms of predicting the control states are achieved for all of the considered topologies

A Data-Driven Approach to Autonomous Management of Photonic Switching System

We propose a data-driven approach based on Machine Learning (ML) to predict control signals of a photonic switching system. The proposed ML agent is trained and tested in a completely topological and technological agnostic way and we envision its application in real-time control-planes

Reconfigurable Optical Interconnections Via Dynamic Computer-Generated Holograms

A system is presented for optically providing one-to-many irregular interconnections, and strength-adjustable many-to-many irregular interconnections which may be provided with strengths (weights) w(sub ij) using multiple laser beams which address multiple holograms and means for combining the beams modified by the holograms to form multiple interconnections, such as a cross-bar switching network. The optical means for interconnection is based on entering a series of complex computer-generated holograms on an electrically addressed spatial light modulator for real-time reconfigurations, thus providing flexibility for interconnection networks for large-scale practical use. By employing multiple sources and holograms, the number of interconnection patterns achieved is increased greatly

Devices and networks for optical switching

This thesis is concerned with some aspects of the application of optics to switching and computing. Two areas are dealt with: the design of switching networks which use optical interconnects, and the development and application of the t-SEED optical logic device. The work on optical interconnects looks at the multistage interconnection network which has been proposed as a hybrid switch using both electronics and optics. It is shown that the architecture can be mapped from one dimensional to two dimensional format, so that the machine makes full use of the space available to the optics. Other mapping rules are described which allow the network to make optimum use of the optical interconnects, and the endpoint is a hybrid optical-electronic machine which should be able to outperform an all-electronic equivalent. The development of the t-SEED optical logic device is described, which is the integration of a phototransistor with a multiple quantum well optical modulator. It is found to be important to have the modulator underneath rather than on top of the transistor to avoid unwanted thyristor action. In order for the transistor to have a high gain the collector must have a low doping level, the exit window in the substrate must be etched all the way to the emitter layer, and the etch must not damage the emitter-base junction. A real optical gain of 1.6 has been obtained, which is higher than has ever been reached before but is not as high as should be possible. Improvements to the device are suggested. A new model of the Fabry-Perot cavity is introduced which helps considerably in the interpretation of experimental measurements made on the quantum well modulators. Also a method of improving the contrast of the multiple quantum well modulator by grading the well widths is proposed which may find application in long wavelength transmission modulators. Some systems which make use of the t-SEED are considered. It is shown that the t-SEED device has the right characteristics for use as a neuron element in the optical implementation of a neural network. A new image processing network for clutter removal in binary images is introduced which uses the t-SEED, and a brief performance analysis suggests that the network may be superior to an all-electronic machine

Machine Learning for Multi-Layer Open and Disaggregated Optical Networks

L'abstract è presente nell'allegato / the abstract is in the attachmen

Spatial parallelism in the routers of asynchronous on-chip networks

State-of-the-art multi-processor systems-on-chip use on-chip networks as their communication fabric. Although most on-chip networks are implemented synchronously, asynchronous on-chip networks have several advantages over their synchronous counterparts. Timing division multiplexing (TDM) flow control methods have been utilized in asynchronous on-chip networks extensively. The synchronization required by TDM leads to significant speed penalties. Compared with using TDM methods, spatial parallelism methods, such as the spatial division multiplexing (SDM) flow control method, achieve better network throughput with less area overhead.This thesis proposes several techniques to increase spatial parallelism in the routers of asynchronous on-chip networks.Channel slicing is a new pipeline structure that alleviates the speed penalty by removing the synchronization among bit-level data pipelines. It is also found out that the lookahead pipeline using early evaluated acknowledgement can be used in routers to further improve speed.SDM is a new flow control method proposed for asynchronous on-chip networks. It improves network throughput without introducing synchronization among buffers of different frames, which is required by TDM methods. It is also found that the area overhead of SDM is smaller than the virtual channel (VC) flow control method -- the most used TDM method. The major design problem of SDM is the area consuming crossbars. A novel 2-stage Clos switch structure is proposed to replace the crossbar in SDM routers, which significantly reduces the area overhead. This Clos switch is dynamically reconfigured by a new asynchronous Clos scheduler.Several asynchronous SDM routers are implemented using these new techniques. An asynchronous VC router is also reproduced for comparison. Performance analyses show that the SDM routers outperform the VC router in throughput, area overhead and energy efficiency.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Automatic Management of N × N Photonic Switch Powered by Machine Learning in Software-Defined Optical Transport

Optical networking is fast evolving towards the applications of the Software-defined Networking (SDN) paradigm down to the (Wavelength-division Multiplexing) WDM transport layer for cost-effective and flexible infrastructure management. Optical SDN requires each network element's software abstraction to enable full control by the centralized network controller. Nowadays, modern network elements, especially photonic switching systems, are developed by exploiting the fast-emerging technology of Photonic Integrated Circuit (PIC) that consists of complex fabrics of elementary units that can be driven individually using a large set of elementary controls. In this work, we focus on modeling the elementary control states of the topological structures behind PIC ${N} \times {N}$ switches under a fully blind approach based on Machine Learning (ML) techniques. The ML agent's training and testing datasets are obtained synthetically by software simulation of the photonic switch structure. The proposed technique's scalability and accuracy are validated by considering different dimensions ${N}$ and applying it to two different switching topologies: the Honey-Comb Rearrangeable Optical Switch and the Benes network. Excellent results in terms of prediction of the control states are achieved for both of the considered topologies

Spatial parallelism in the routers of asynchronous on-chip networks

State-of-the-art multi-processor systems-on-chip use on-chip networks as their communication fabric. Although most on-chip networks are implemented synchronously, asynchronous on-chip networks have several advantages over their synchronous counterparts. Timing division multiplexing (TDM) flow control methods have been utilized in asynchronous on-chip networks extensively. The synchronization required by TDM leads to significant speed penalties. Compared with using TDM methods, spatial parallelism methods, such as the spatial division multiplexing (SDM) flow control method, achieve better network throughput with less area overhead.This thesis proposes several techniques to increase spatial parallelism in the routers of asynchronous on-chip networks.Channel slicing is a new pipeline structure that alleviates the speed penalty by removing the synchronization among bit-level data pipelines. It is also found out that the lookahead pipeline using early evaluated acknowledgement can be used in routers to further improve speed.SDM is a new flow control method proposed for asynchronous on-chip networks. It improves network throughput without introducing synchronization among buffers of different frames, which is required by TDM methods. It is also found that the area overhead of SDM is smaller than the virtual channel (VC) flow control method -- the most used TDM method. The major design problem of SDM is the area consuming crossbars. A novel 2-stage Clos switch structure is proposed to replace the crossbar in SDM routers, which significantly reduces the area overhead. This Clos switch is dynamically reconfigured by a new asynchronous Clos scheduler.Several asynchronous SDM routers are implemented using these new techniques. An asynchronous VC router is also reproduced for comparison. Performance analyses show that the SDM routers outperform the VC router in throughput, area overhead and energy efficiency.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Dynamic element matching techniques for data converters

Analog to digital converter (ADC) circuit component errors create nonuniform quantization code widths and create harmonic distortion in an ADC\u27s output. In this dissertation, two techniques for estimating an ADC\u27s output spectrum from the ADC\u27s transfer function are determined. These methods are compared to a symmetric power function and asymmetric power function approximations. Standard ADC performance metrics, such as SDR, SNDR, SNR, and SFDR, are also determined as a function of the ADC\u27s transfer function approximations. New dynamic element matching (DEM) flash ADCs are developed. An analysis of these DEM flash ADCs is developed and shows that these DEM algorithms improve an ADC\u27s performance. The analysis is also used to analyze several existing DEM ADC architectures; Digital to analog converter (DAC) circuit component errors create nonuniform quantization code widths and create harmonic distortion in a DAC\u27s output. In this dissertation, an exact relationship between a DAC\u27s integral nonlinearity (INL) and its output spectrum is determined. Using this relationship, standard DAC performance metrics, such as SDR, SNDR, SNR, and SFDR, are calculated from the DAC\u27s transfer function. Furthermore, an iterative method is developed which determines an arbitrary DAC\u27s transfer function from observed output magnitude spectra. An analysis of DEM techniques for DACs, including the determination of several suitable metrics by which DEM techniques can be compared, is derived. The performance of a given DEM technique is related to standard DAC performance metrics, such as SDR, SNDR, and SFDR. Conditions under which DEM techniques can guarantee zero average INL and render the distortion due to mismatched components as white noise are developed. Several DEM circuits proposed in the literature are shown to be equivalent and have hardware efficient implementations based on multistage interconnection networks. Example DEM circuit topologies and their hardware efficient VLSI implementations are also presented