LOW LEAKAGE CHARGE RECYCLING TECHNIQUE FOR POWER MINIMIZATION IN CNTFET CIRCUITS

Carbon Nanotube Field Effect Transistor (CNTFET) is one of the most promising candidates in the near future for digital design due to its better electrostatics and higher mobility characteristics. Parameters that determine the CNTFET performance are the number of tubes, pitch, diameter and oxide thickness. In this paper, a power gating design methodology to realise low power CNTFET digital circuits even under device parameter changes is presented. Investigation about the effect of different CNTFET parameters on dynamic and standby power is carried out. Simulation results reveal that the power gated circuits suppress a maximum of about 67% dynamic power and 59% standby power compared to conventional circuits

Circuit-level modelling and simulation of carbon nanotube devices

The growing academic interest in carbon nanotubes (CNTs) as a promising novel class of electronic materials has led to significant progress in the understanding of CNT physics including ballistic and non-ballistic electron transport characteristics. Together with the increasing amount of theoretical analysis and experimental studies into the properties of CNT transistors, the need for corresponding modelling techniques has also grown rapidly. This research is focused on the electron transport characteristics of CNT transistors, with the aim to develop efficient techniquesto model and simulate CNT devices for logic circuit analysis.The contributions of this research can be summarised as follows. Firstly, to accelerate the evaluation of the equations that model a CNT transistor, while maintaining high modelling accuracy, three efficient numerical techniques based on piece-wise linear, quadratic polynomial and cubic spline approximation have been developed. The numerical approximation simplifies the solution of the CNT transistor’s self-consistent voltage such that the calculation of the drain-source current is accelerated by at least two orders of magnitude. The numerical approach eliminates complicated calculations in the modelling process and facilitates the development of fast and efficient CNT transistor models for circuit simulation.Secondly, non-ballistic CNT transistors have been considered, and extended circuit-level models which can capture both ballistic and non-ballistic electron transport phenomena, including elastic scattering, phonon scattering, strain and tunnelling effects, have been developed. A salient feature of the developed models is their ability to incorporate both ballistic and non-ballistic transport mechanisms without a significant computational cost. The developed models have been extensively validated against reported transport theories of CNT transistors and experimental results.Thirdly, the proposed carbon nanotube transistor models have been implemented on several platforms. The underlying algorithms have been developed and tested in MATLAB, behaviourallevel models in VHDL-AMS, and improved circuit-level models have been implemented in two versions of the SPICE simulator. As the final contribution of this work, parameter variation analysis has been carried out in SPICE3 to study the performance of the proposed circuit-level CNT transistor models in logic circuit analysis. Typical circuits, including inverters and adders, have been analysed to determine the dependence of the circuit’s correct operation on CNT parameter variation

Novel High Performance Ultra Low Power Static Random Access Memories (SRAMs) Based on Next Generation Technologies

Title from PDF of title page viewed January 27, 2021Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (page 107-120)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2019Next Big Thing Is Surely Small: Nanotechnology Can Bring Revolution. Nanotechnology leads the world towards many new applications in various fields of computing, communication, defense, entertainment, medical, renewable energy and environment. These nanotechnology applications require an energy-efficient memory system to compute and process. Among all the memories, Static Random Access Memories (SRAMs) are high performance memories and occupies more than 50% of any design area. Therefore, it is critical to design high performance and energy-efficient SRAM design. Ultra low power and high speed applications require a new generation memory capable of operating at low power as well as low execution time. In this thesis, a novel 8T SRAM design is proposed that offers significantly faster access time and lowers energy consumption along with better read stability and write ability. The proposed design can be used in the conventional SRAM as well as in computationally intensive applications like neural networks and machine learning classifiers [1]-[4]. Novel 8T SRAM design offers higher energy efficiency, reliability, robustness and performance compared to the standard 6T and other existing 8T and 9T designs. It offers the advantages of a 10T SRAM without the additional area, delay and power overheads of the 10T SRAM. The proposed 8T SRAM would be able to overcome many other limitations of the conventional 6T and other 7T, 8T and 9T designs. The design employs single bitline for the write operation, therefore the number of write drivers are reduced. The defining feature of the proposed 8T SRAM is its hybrid design, which is the combination of two techniques: (i) the utilization of single-ended bitline and (ii) the utilization of virtual ground. The single-ended bitline technique ensures separate read and write operations, which eventually reduces the delay and power consumption during the read and write operations. It's independent read and write paths allow the use of the minimum sized access transistors and aid in a disturb-free read operation. The virtual ground weakens the positive feedback in the SRAM cell and improves its write ability. The virtual ground technique is also used to reduce leakages. The proposed design does not require precharging the bitlines for the read operation, which reduces the area and power overheads of the memory system by eliminating the precharging circuit. The design isolates the storage node from the read path, which improves the read stability. For reliability study, we have investigated the static noise margin (SNM) of the proposed 8T SRAM, for which, we have used two methods – (i) the traditional SNM method with the butterfly curve, (ii) the N-curve method A comparative analysis is performed between the proposed and the existing SRAM designs in terms of area, total power consumption during the read and write operations, and stability and reliability. All these advantages make the proposed 8T SRAM design an ideal candidate for the conventional and computationally intensive applications like machine learning classifier and deep learning neural network. In addition to this, there is need for next generation technologies to design SRAM memory because the conventional CMOS technology is approaching its physical and performance boundaries and as a consequence, becoming incompatible with ultra-low-power applications. Emerging devices such as Tunnel Field Effect Transistor (TFET)) and Graphene Nanoribbon Field Effect Transistor (GNRFET) devices are highly potential candidates to overcome the limitations of MOSFET because of their ability to achieve subthreshold slopes below 60 mV/decade and very low leakage currents [6]-[9]. This research also explores novel TFET and GNRFET based 6T SRAM. The thesis evaluates the standby leakage power in the Tunnel FET (TFET) based 6T SRAM cell for different pull-up, pull-down, and pass-gate transistors ratios (PU: PD: PG) and compared to 10nm FinFET based 6T SRAM designs. It is observed that the 10nm TFET based SRAMs have 107.57%, 163.64%, and 140.44% less standby leakage power compared to the 10nm FinFET based SRAMs when the PU: PD: PG ratios are 1:1:1, 1:5:2 and 2:5:2, respectively. The thesis also presents an analysis of the stability and reliability of sub-10nm TFET based 6T SRAM circuit with a reduced supply voltage of 500mV. The static noise margin (SNM), which is a critical measure of SRAM stability and reliability, is determined for hold, read and write operations of the 6T TFET SRAM cell. The robustness of the optimized TFET based 6T SRAM circuit is also evaluated at different supply voltages. Simulations were done in HSPICE and Cadence tools. From the analysis, it is clear that the main advantage of the TFET based SRAM would be the significant improvement in terms of leakage or standby power consumption. Compared to the FinFET based SRAM the standby leakage power of the T-SRAMs are 107.57%, 163.64%, and 140.44% less for 1:1:1, 1:5:2 and 2:5:2 configurations, respectively. Since leakage/standby power is the primary source of power consumption in the SRAM, and the overall system energy efficiency depends on SRAM power consumption, TFET based SRAM would lead to massive improvement of the energy efficiency of the system. Therefore, T-SRAMs are more suitable for ultra-low power applications. In addition to this, the thesis evaluates the standby leakage power of types of Graphene Nanoribbon FETs based 6T SRAM bitcell and compared to 10nm FinFET based 6T SRAM bitcell. It is observed that the 10nm MOS type GNRFET based SRAMs have 16.43 times less standby leakage power compared to the 10nm FinFET based SRAMs. The double gate SB-GNRFET based SRAM consumes 1.35E+03 times less energy compared to the 10nm FinFET based SRAM during write. However, during read double gate SB-GNRFET based SRAM consume 15 times more energy than FinFET based SRAM. It is also observed that GNRFET based SRAMs are more stable and reliable than FinFET based SRAM.Introduction -- Background -- Novel High Performance Ultra Low Power SRAM Design -- Tunnel FET Based SRAM Design -- Graphene Nanoribbon FET Based SRAM Design -- Double-gate FDSOI Based SRAM Designs -- Novel CNTFET and MEMRISTOR Based Digital Designs -- Conclusio

Silicon on ferroelectric insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

Title from PDF of title page, viewed on March 12, 2014Thesis advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 116-131)Thesis (M. S.)--School of Computer and Engineering. University of Missouri--Kansas City, 2013Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in subnanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor’s Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-lowpower applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.Abstract -- List of illustrations - List of tables -- Acknowledgements -- Dedication -- Introduction -- Carbon nanotube field effect transistor -- Multi-gate transistors -FinFET -- Subthreshold swing -- Tunneling field effect transistors -- I-mos and nanowire fets -- Ferroelectric based field effect transistors -- An analytical model to approximate the subthreshold swing for soi-finfet -- Silicon-on-ferroelectric insulator field effect transistor (SOF-FET) -- Current-voltage characteristics of sof-fet -- Advantages, manufacturing process and future work of the proposed device -- Appendix -- Reference

Ultra-Low Power Ternary CMOS Platform for Physical Synthesis of Multi-Valued Logic and Memory Applications

Department of Electrical EngineeringMotivation of this work is to provide feasible, scalable, and designable multi-valued logic (MVL) device platform for physical synthesis of MVL circuits. Especially, ternary device and its general logic functions are focused, owing to most efficiently reduced circuit complexity per radix (R) increase. By designing the OFF-state constant current, not only the standby power (PS) issue of additional intermediate state is overcome, but also continuous supply voltage (VDD) scaling and dynamic power (PD) scaling are possible owing to single-step I-V characteristics. By applying a novel ternary device concept to CMOS technology with OFF-state current mechanism of band-to-band tunneling (BTBT) currents (IBTBT) and subthreshold diffusion current (Isub), the logic changes from binary to ternary are confirmed using mixed-mode device simulation. I experimentally demonstrate ternary CMOS (T-CMOS) and verified its low-power standard ternary inverter (STI) operation by designing channel profiles in conventional binary CMOS. The realized complementary ternary n/pMOS (T-n/pMOS) have fully gate bias (VG)-independent and symmetrical IBTBT of ~10 pA/???m based on proven ion-implantation process, which produces stable and designable intermediate state (VOM) at exactly VDD/2. To present T-CMOS design frameworks in terms of static noise margin (SNM) enhancement and ultra-low power operation, I develop the compact model of T-CMOS and verify the physical model parameters with experimental data. Through the feasible design of Isub with abrupt channel profile based on low thermal budget process, STI has a SNM of 283 mV (80 % of ideal SNM) at VDD= 1V operation and intermediate state stability of ??VOM < ?? 0.1V, even considering the random-dopant fluctuation (RDF) of 32 nm and 22 nm technology. Continuous VDD scaling below 0.5V (SNM= 40% at VDD = 0.3V) enables STI operation with ultra-low PD and PS based on exponentially reduced IBTBT currents. As MVL and memory (MVM) applications, minimum(MIN)/maximum(MAX) gates, analog-to-digital converter (ADC) circuit, and 5-state latch are studied with T-CMOS compact model. Especially ADC circuits revolutionary decreases number of device and circuit interconnection with 9.6% area of binary system.ope

Technological Solution beyond MOSFET and Binary Logic Device

Title from PDF of title page viewed January 31, 2019Thesis advisor: Masud ChowdhuryVitaIncludes bibliographical references (pages 64-70)Thesis (M.S.)--School of Computing and Engineering, University of Missouri--Kansas City, 2018Today’s technology is based on the binary number system-based circuitry, which is the outcome of the simple on and off switching mechanism of the prevailing transistors. Consideration of higher radix number system can eradicate or lessen many limitations of binary number system such as the saturation of Moore’s law. The most substantial potential benefits of higher radix approaches are the decrease of wiring complexity. Excessive scaling of the technologies has led the researchers beyond Binary Logic and MOSFET technology. TFET considered as one of the most promising options for low-power application for beyond MOSFET technologies. Graphene Nano Ribbon, due to its high-carrier mobility, tunable bandgap and its outstanding electrostatic control of device gate becomes ideal choice for channel material of TFET. This paper proposes double gated ultra-thin body (UTB) TFET device model using Graphene nano ribbon as the channel material. In this paper evaluation of the model by performing the comparative analysis with InAs as the channel material in terms of Ec-Ev on and off state and Id-Vg characteristics is presented. The feasibility of multi valued logic system in real-world rests on two serious aspects, such as, the easiness of mathematical approach for implementing the multivalued logic into today’s technology and the sufficiency of synthesis techniques. In this paper, we have focused on the different technology available for implementing multivalued logic especially ternary logic. Ternary logic devices are expected to lead to an exponential increase of the information handling capability, which binary logic cannot support. Memory capacitor or memcapacitor is an emerging device that exhibits hysteresis behavior, which can be manipulated by external parameters, such as, the applied electric field or voltage. One of the unique properties of the memcapacitor is that by using the percolation approach, we can achieve Metal-Insulator-Transition (MIT) phenomenon, which can be utilized to obtain a staggered hysteresis loop. For multivalued logic devices staggered hysteresis behavior is the critical requirement. In this paper, we propose a new conceptual design of a ternary logic device by vertically stacking dielectric material interleaved with layers of graphene nanoribbon (GNR) between two external metal plates. The proposed device structure displays the memcapacitive behavior with the fast switching metal-to-insulator transition in picosecond scale. The device model is later extended into a vertical-cascaded version, which acts as a ternary device.Introduction -- Multi valued logic -- Overview of different MVL technologies -- Graphene memcapacitor based ternary logic device -- Graphene nano ribbon based TFET -- Conclusion and future wor

Schottky Field Effect Transistors and Schottky CMOS Circuitry

It was the primary goal (and result) of the presented work to empirically demonstrate CMOS operation (i.e., inverter transfer characteristics) using metallic/Schottky source/drain MOSFETs (SFETs - Schottky Field Effect Transistors) fabricated on silicon-on-insulator (SOI) substrates - a first-ever in the history of SFET research. Due to its candidacy for present and future CMOS technology, many different research groups have explored different SFET architectures in an effort to maximize performance. In the presented work, an architecture known as a bulk switching SFET was fabricated using an implant-to-silicide (ITS) technique, which facilitates a high degree of Schottky barrier lowering and therefore an increase in current injection with minimal process complexity. The different switching mechanism realized with this technique also reduces the ambipolar leakage current that has so often plagued SFETs of more conventional design. In addition, these devices have been utilized in a patent pending approach that may facilitate an increase in circuit density for devices of a given size. In other words, for example, it may be possible to achieve circuit density equivalent to 65 nm technology using a 90 nm process, while at the same time preserving or reducing local interconnect density for enhanced overall system speed. Fabrication details and electrical results will be discussed, as well as some initial modeling efforts toward gaining insight into the details of current injection at the metal-semiconductor (M-S) interface. The challenges faced using the ITS approach at aggressive scales will be discussed, as will the potential advantages and disadvantages of other approaches to SFET technology

Imperfection-Aware Design of CNFET Digital VLSI Circuits

Carbon nanotube field-effect transistor (CNFET) is one of the promising candidates as extensions to silicon CMOS devices. The CNFET, which is a 1-D structure with a near-ballistic transport capability, can potentially offer excellent device characteristics and order-of-magnitude better energy-delay product over standard CMOS devices. Significant challenges in CNT synthesis prevent CNFETs today from achieving such ideal benefits. CNT density variation and metallic CNTs are the dominant type of CNT variations/imperfections that cause performance variation, large static power consumption, and yield degradation. We present an imperfection-aware design technique for CNFET digital VLSI circuits by: 1) Analytical models that are developed to analyze and quantify the effects of CNT density variation on device characteristics, gate and system levels delays. The analytical models, which were validated by comparison to real experimental/simulation data, enables us to examine the space of CNFET combinational, sequential and memory cells circuits to minimize delay variations. Using these model, we drive CNFET processing and circuit design guidelines to manage/overcome CNT density variation. 2) Analytical models that are developed to analyze the effects of metallic CNTs on device characteristics, gate and system levels delay and power consumption. Using our presented analytical models, which are again validated by comparison with simulation data, it is shown that the static power dissipation is a more critical issue than the delay and the dynamic power of CNFET circuits in the presence of m-CNTs. 3) CNT density variation and metallic CNTs can result in functional failure of CNFET circuits. The complete and compact model for CNFET probability of failure that consider CNT density variation and m-CNTs is presented. This analytical model is applied to analyze the logical functional failures. The presented model is extended to predict opportunities and limitations of CNFET technology at todays Gigascale integration and beyond.\u2

Optimization of CNFET Parameters for High Performance Digital Circuits

The Carbon Nanotube Field Effect Transistor (CNFET) is one of the most promising candidates to become successor of silicon CMOS in the near future because of its better electrostatics and higher mobility. The CNFET has many parameters such as operating voltage, number of tubes, pitch, nanotube diameter, dielectric constant, and contact materials which determine the digital circuit performance. This paper presents a study that investigates the effect of different CNFET parameters on performance and proposes a new CNFET design methodology to optimize performance characteristics such as current driving capability, delay, power consumption, and area for digital circuits. We investigate and conceptually explain the performance measures at 32 nm technologies for pure-CNFET, hybrid MOS-CNFET, and CMOS configurations. In our proposed design methodology, the power delay product (PDP) of the optimized CNFET is about 68%, 63%, and 79% less than that of the nonoptimized CNFET, hybrid MOS-CNFET, and CMOS circuits, respectively. Therefore, the proposed CNFET design is a strong candidate to implement high performance digital circuits

Cross-Layer Resiliency Modeling and Optimization: A Device to Circuit Approach

The never ending demand for higher performance and lower power consumption pushes the VLSI industry to further scale the technology down. However, further downscaling of technology at nano-scale leads to major challenges. Reduced reliability is one of them, arising from multiple sources e.g. runtime variations, process variation, and transient errors. The objective of this thesis is to tackle unreliability with a cross layer approach from device up to circuit level