Adaptive overcurrent protection application for a micro-grid system in South Africa

Abstract: The non-directional overcurrent protection (International Electrotechnical Commission standard IEC 617 or American National Standards Institute ANSI/Institute of Electrical and Electronic Engineers IEEE C37.2 standard device number 51) is one protection type/relay function that has stood the test of time. The latest generation of relays has brought about enhanced capabilities. The most popular overcurrent protection, which is the Inverse Definite Minimum Time (IDMT) function, has proven to provide coordination of electrical nodes with ease. This is one of the oldest but extremely reliable relay characteristic. A number of new protection functions and enhancements to existing functions are commensurate to the advanced technical capabilities of the newer generation protective devices. The new development techniques include “acceleration”, which is a technique of sending the circuit breaker status of the near end of a line or feeder to the far end to influence the relay decision at the far end. Impedance protection, unit line protection, etc. have come with many advanced characteristics and properties. The enhancements to protection devices bear special features but cannot substitute inverse time overcurrent protection, which, up to now, is a reliable backup in feeder protection schemes in South Africa. The superior feature is the capability to achieve coordination between a series of protective devices. This is achievable without excessive damage to the electrical components of the circuit...M.Ing. (Electrical Engineering

Voltage drop tolerance by adaptive voltage scaling using clock-data compensation

Proyecto de Graduación (Maestría en Ingeniería en Electrónica) Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica, 2019.El ruido de alta frecuencia en la red de alimentación compromete el rendimiento y la eficiencia energética de los sistemas electrónicos con microprocesadores, restringiendo la frecuencia máxima de operación de los sistemas y disminuyendo la confiabilidad de los dispositivos. La frecuencia máxima será determinada por la ruta de datos más crítica (la ruta de datos más lenta). De esta manera, es necesario configurar una banda de guarda para tolerar caídas de voltaje sin tener ningún problema de ejecución, pero sacrificando el rendimiento eléctrico. Este trabajo evalúa el impacto de la caída de voltaje en el rendimiento de los circuitos CMOS de alta densidad, estableciendo un conjunto de casos de prueba que contienen diferentes configuraciones de circuitos. Se desarrolló una técnica adaptable y escalable para mejorar la tolerancia a la caída de voltaje en los circuitos CMOS a través del escalado adaptativo, aprovechando el efecto de compensación de datos del reloj. La solución propuesta se validó aplicándola a diferentes casos de prueba en una tecnología FinFet-CMOS a nivel de simulación del diseño físico.High-frequency power supply noise compromises performance and energy efficiency of microprocessor-based products, restricting the maximum frequency of operation for electronic systems and decreasing device reliability. The maximum frequency is going to be determine by the most critical data path (the slowest data path). In this way, a guard band needs to be set in order to tolerate voltage drops without having any execution problem, but leading to a performance reduction. This work evaluates the impact of voltage drop in the performance of CMOS circuits by establishing a set of test cases containing different circuit configurations. An adaptive and scalable technique is proposed to enhance voltage drop tolerance in CMOS circuits through adaptive scaling, taking advantage of the clock-data compensation effect. The proposed solution is validated by applying it to different test cases in a FinFet CMOS technology at a post-layout simulation level

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

With the omnipresence of embedded processing in all forms of electronics today, there is a strong trend towards wireless, battery-powered, portable embedded systems which have to operate under stringent energy constraints. Consequently, low power consumption and high energy efficiency have emerged as the two key criteria for embedded microprocessor design. In this thesis we present a range of microarchitectural low-power design techniques which enable the increase of performance for embedded microprocessors and/or the reduction of energy consumption, e.g., through voltage scaling. In the context of cryptographic applications, we explore the effectiveness of instruction set extensions (ISEs) for a range of different cryptographic hash functions (SHA-3 candidates) on a 16-bit microcontroller architecture (PIC24). Specifically, we demonstrate the effectiveness of light-weight ISEs based on lookup table integration and microcoded instructions using finite state machines for operand and address generation. On-node processing in autonomous wireless sensor node devices requires deeply embedded cores with extremely low power consumption. To address this need, we present TamaRISC, a custom-designed ISA with a corresponding ultra-low-power microarchitecture implementation. The TamaRISC architecture is employed in conjunction with an ISE and standard cell memories to design a sub-threshold capable processor system targeted at compressed sensing applications. We furthermore employ TamaRISC in a hybrid SIMD/MIMD multi-core architecture targeted at moderate to high processing requirements (> 1 MOPS). A range of different microarchitectural techniques for efficient memory organization are presented. Specifically, we introduce a configurable data memory mapping technique for private and shared access, as well as instruction broadcast together with synchronized code execution based on checkpointing. We then study an inherent suboptimality due to the worst-case design principle in synchronous circuits, and introduce the concept of dynamic timing margins. We show that dynamic timing margins exist in microprocessor circuits, and that these margins are to a large extent state-dependent and that they are correlated to the sequences of instruction types which are executed within the processor pipeline. To perform this analysis we propose a circuit/processor characterization flow and tool called dynamic timing analysis. Moreover, this flow is employed in order to devise a high-level instruction set simulation environment for impact-evaluation of timing errors on application performance. The presented approach improves the state of the art significantly in terms of simulation accuracy through the use of statistical fault injection. The dynamic timing margins in microprocessors are then systematically exploited for throughput improvements or energy reductions via our proposed instruction-based dynamic clock adjustment (DCA) technique. To this end, we introduce a 6-stage 32-bit microprocessor with cycle-by-cycle DCA. Besides a comprehensive design flow and simulation environment for evaluation of the DCA approach, we additionally present a silicon prototype of a DCA-enabled OpenRISC microarchitecture fabricated in 28 nm FD-SOI CMOS. The test chip includes a suitable clock generation unit which allows for cycle-by-cycle DCA over a wide range with fine granularity at frequencies exceeding 1 GHz. Measurement results of speedups and power reductions are provided

Microcomputer based controller for the Langley 0.3-meter Transonic Cryogenic Tunnel

Flow control of the Langley 0.3-meter Transonic Cryogenic Tunnel (TCT) is a multivariable nonlinear control problem. Globally stable control laws were generated to hold tunnel conditions in the presence of geometrical disturbances in the test section and precisely control the tunnel states for small and large set point changes. The control laws are mechanized as four inner control loops for tunnel pressure, temperature, fan speed, and liquid nitrogen supply pressure, and two outer loops for Mach number and Reynolds number. These integrated control laws have been mechanized on a 16-bit microcomputer working on DOS. This document details the model of the 0.3-m TCT, control laws, microcomputer realization, and its performance. The tunnel closed loop responses to small and large set point changes were presented. The controller incorporates safe thermal management of the tunnel cooldown based on thermal restrictions. The controller was shown to provide control of temperature to + or - 0.2K, pressure to + or - 0.07 psia, and Mach number to + or - 0.002 of a given set point during aerodynamic data acquisition in the presence of intrusive geometrical changes like flexwall movement, angle-of-attack changes, and drag rake traverse. The controller also provides a new feature of Reynolds number control. The controller provides a safe, reliable, and economical control of the 0.3-m TCT

Design of variability compensation architectures of digital circuits with adaptive body bias

The most critical concern in circuit is to achieve high level of performance with very tight power constraint. As the high performance circuits moved beyond 45nm technology one of the major issues is the parameter variation i.e. deviation in process, temperature and voltage (PVT) values from nominal specifications. A key process parameter subject to variation is the transistor threshold voltage (Vth) which impacts two important parameters: frequency and leakage power. Although the degradation can be compensated by the worstcase scenario based over-design approach, it induces remarkable power and performance overhead which is undesirable in tightly constrained designs. Dynamic voltage scaling (DVS) is a more power efficient approach, however its coarse granularity implies difficulty in handling fine grained variations. These factors have contributed to the growing interest in power aware robust circuit design. We propose a variability compensation architecture with adaptive body bias, for low power applications using 28nm FDSOI technology. The basic approach is based on a dynamic prediction and prevention of possible circuit timing errors. In our proposal we are using a Canary logic technique that enables the typical-case design. The body bias generation is based on a DLL type method which uses an external reference generator and voltage controlled delay line (VCDL) to generate the forward body bias (FBB) control signals. The adaptive technique is used for dynamic detection and correction of path failures in digital designs due to PVT variations. Instead of tuning the supply voltage, the key idea of the design approach is to tune the body bias voltage bymonitoring the error rate during operation. The FBB increases operating speed with an overhead in leakage power

Tunneling Horizontal IEC 61850 Traffic through Audio Video Bridging Streams for Flexible Microgrid Control and Protection

In this paper, it is argued that some low-level aspects of the usual IEC 61850 mapping to Ethernet are not well suited to microgrids due to their dynamic nature and geographical distribution as compared to substations. It is proposed that the integration of IEEE time-sensitive networking (TSN) concepts (which are currently implemented as audio video bridging (AVB) technologies) within an IEC 61850 / Manufacturing Message Specification framework provides a flexible and reconfigurable platform capable of overcoming such issues. A prototype test platform and bump-in-the-wire device for tunneling horizontal traffic through AVB are described. Experimental results are presented for sending IEC 61850 GOOSE (generic object oriented substation events) and SV (sampled values) messages through AVB tunnels. The obtained results verify that IEC 61850 event and sampled data may be reliably transported within the proposed framework with very low latency, even over a congested network. It is argued that since AVB streams can be flexibly configured from one or more central locations, and bandwidth reserved for their data ensuring predictability of delivery, this gives a solution which seems significantly more reliable than a pure MMS-based solution

Very-Large-Scale-Integration Circuit Techniques in Internet-of-Things Applications

Heading towards the era of Internet-of-things (IoT) means both opportunity and challenge for the circuit-design community. In a system where billions of devices are equipped with the ability to sense, compute, communicate with each other and perform tasks in a coordinated manner, security and power management are among the most critical challenges. Physically unclonable function (PUF) emerges as an important security primitive in hardware-security applications; it provides an object-specific physical identifier hidden within the intrinsic device variations, which is hard to expose and reproduce by adversaries. Yet, designing a compact PUF robust to noise, temperature and voltage remains a challenge. This thesis presents a novel PUF design approach based on a pair of ultra-compact analog circuits whose output is proportional to absolute temperature. The proposed approach is demonstrated through two works: (1) an ultra-compact and robust PUF based on voltage-compensated proportional-to-absolute-temperature voltage generators that occupies 8.3× less area than the previous work with the similar robustness and twice the robustness of the previously most compact PUF design and (2) a technique to transform a 6T-SRAM array into a robust analog PUF with minimal overhead. In this work, similar circuit topology is used to transform a preexisting on-chip SRAM into a PUF, which further reduces the area in (1) with no robustness penalty. In this thesis, we also explore techniques for power management circuit design. Energy harvesting is an essential functionality in an IoT sensor node, where battery replacement is cost-prohibitive or impractical. Yet, existing energy-harvesting power management units (EH PMU) suffer from efficiency loss in the two-step voltage conversion: harvester-to-battery and battery-to-load. We propose an EH PMU architecture with hybrid energy storage, where a capacitor is introduced in addition to the battery to serve as an intermediate energy buffer to minimize the battery involvement in the system energy flow. Test-case measurements show as much as a 2.2× improvement in the end-to-end energy efficiency. In contrast, with the drastically reduced power consumption of IoT nodes that operates in the sub-threshold regime, adaptive dynamic voltage scaling (DVS) for supply-voltage margin removal, fully on-chip integration and high power conversion efficiency (PCE) are required in PMU designs. We present a PMU–load co-design based on a fully integrated switched-capacitor DC-DC converter (SC-DC) and hybrid error/replica-based regulation for a fully digital PMU control. The PMU is integrated with a neural spike processor (NSP) that achieves a record-low power consumption of 0.61 µW for 96 channels. A tunable replica circuit is added to assist the error regulation and prevent loss of regulation. With automatic energy-robustness co-optimization, the PMU can set the SC-DC’s optimal conversion ratio and switching frequency. The PMU achieves a PCE of 77.7% (72.2%) at VIN = 0.6 V (1 V) and at the NSP’s margin-free operating point

Energy autonomous systems : future trends in devices, technology, and systems

The rapid evolution of electronic devices since the beginning of the nanoelectronics era has brought about exceptional computational power in an ever shrinking system footprint. This has enabled among others the wealth of nomadic battery powered wireless systems (smart phones, mp3 players, GPS, …) that society currently enjoys. Emerging integration technologies enabling even smaller volumes and the associated increased functional density may bring about a new revolution in systems targeting wearable healthcare, wellness, lifestyle and industrial monitoring applications

Mission management, planning, and cost: PULSE Attitude And Control Systems (AACS)

The Pluto unmanned long-range scientific explorer (PULSE) is a probe that will do a flyby of Pluto. It is a low weight, relatively low costing vehicle which utilizes mostly off-the-shelf hardware, but not materials or techniques that will be available after 1999. A design, fabrication, and cost analysis is presented. PULSE will be launched within the first decade of the twenty-first century. The topics include: (1) scientific instrumentation; (2) mission management, planning, and costing; (3) power and propulsion systems; (4) structural subsystem; (5) command, control, and communication; and (6) attitude and articulation control