Sizing up nanoelectronics: gauging the potential for new productivity wave

The Federal Reserve Bank of Dallas, in cooperation with the Semiconductor Industry Association (SIA), hosted a conference on nanoelectronics and the economy in Austin on Dec. 3, 2010. Economists and scientists explored how information technology has affected U.S. productivity and output growth and prospects for the future.Technological innovations ; Productivity

ToPoliNano: Nanoarchitectures Design Made Real

Many facts about emerging nanotechnologies are yet to be assessed. There are still major concerns, for instance, about maximum achievable device density, or about which architecture is best fit for a specific application. Growing complexity requires taking into account many aspects of technology, application and architecture at the same time. Researchers face problems that are not new per se, but are now subject to very different constraints, that need to be captured by design tools. Among the emerging nanotechnologies, two-dimensional nanowire based arrays represent promising nanostructures, especially for massively parallel computing architectures. Few attempts have been done, aimed at giving the possibility to explore architectural solutions, deriving information from extensive and reliable nanoarray characterization. Moreover, in the nanotechnology arena there is still not a clear winner, so it is important to be able to target different technologies, not to miss the next big thing. We present a tool, ToPoliNano, that enables such a multi-technological characterization in terms of logic behavior, power and timing performance, area and layout constraints, on the basis of specific technological and topological descriptions. This tool can aid the design process, beside providing a comprehensive simulation framework for DC and timing simulations, and detailed power analysis. Design and simulation results will be shown for nanoarray-based circuits. ToPoliNano is the first real design tool that tackles the top down design of a circuit based on emerging technologie

From Microelectronics to Nanoelectronics: Introducing Nanotechnology to VLSI Curricula

© 2011 by ASEEIn the past decades, VLSI industries constantly shrank the size of transistors, so that more and more transistors can be built into the same chip area to make VLSI more and more powerful in its functions. As the typical feature size of CMOS VLSI is shrunk into deep submicron domain, nanotechnology is the next step in order to maintain Moore’s law for several more decades. Nanotechnology not only further improves the resolution in traditional photolithography process, but also introduces many brand-new fabrication strategies, such as bottom-up molecular self-assembly. Nanotechnology is also enabling many novel devices and circuit architectures which are totally different from current microelectronics circuits, such as quantum computing, nanowire crossbar circuits, spin electronics, etc. Nanotechnology is bringing another technology revolution to traditional CMOS VLSI technology. In order to train students to meet the quickly-increasing industry demand for nextgeneration nanoelectronics engineers, we are making efforts to introduce nanotechnology into our VLSI curricula. We have developed a series of VLSI curricula which include CPE/EE 448D - Introduction to VLSI, EE 548 - Low Power VLSI Circuit Design, EE 458 - Analog VLSI Circuit Design, EE 549 - VLSI Testing, etc. Furthermore, we developed a series of micro and nanotechnology related courses, such as EE 451 - Nanotechnology, EE 448 - Microelectronic Fabrication, EE 446 – MEMS (Microelectromechanical Systems). We introduce nanotechnology into our VLSI curricula, and teach the students about various devices, fabrication processes, circuit architectures, design and simulation skills for future nanotechnology-based nanoelectronic circuits. Some examples are nanowire crossbar circuit architecture, carbon-nanotube based nanotransistor, single-electron transistor, spintronics, quantum computing, bioelectronic circuits, etc. Students show intense interest in these exciting topics. Some students also choose nanoelectronics as the topic for their master project/thesis, and perform successful research in the field. The program has attracted many graduate students into the field of nanoelectronics

DC and radio-frequency transmission characteristics of double-walled carbon nanotubes-based ink

In this paper, double-walled carbon nanotubes (DWNTs) network layers were patterned using inkjet transfer printing. The remarkable conductive characteristics of carbon nanotubes (CNTs) are considered as promising candidates for transmission line as well as microelectronic interconnects of an arbitrary pattern. In this work, the DWNTs were prepared by the catalytic chemical vapor deposition process, oxidized and dispersed in ethylene glycol solution. The DWNTs networks were deposited between electrodes contact and then characterized at DC through current-voltage measurements, low frequency, and high frequency by scattering parameters measurements from 40 MHz up to 40 GHz through a vector network analyzer. By varying the number of inkjet overwrites, the results confirm that the DC resistance of DWNTs networks can be varied according to their number and that furthermore the networks preserve ohmic characteristics up to 100 MHz. The microwave transmission parameters were obtained from the measured S-parameter data. An algorithm is developed to calculate the propagation constant "γ", attenuation constant "α" in order to show the frequency dependence of the equivalent resistance of DWNTs networks, which decreases with increasing frequency

Monte Carlo simulations of high-performance implant free In_0.3Ga_0.7 nano-MOSFETs for low-power CMOS applications

No abstract available