A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices

Electrical performance and reliability characterization of a SiC MOSFET power module with embedded decoupling capacitors

Integration of decoupling capacitors in SiC MOSFET modules is an advanced solution to mitigate the effect of parasitic inductance induced by module assembly interconnects. In this paper, the switching transient behavior is reported for a 1.2kV SiC MOSFET module with embedded DC-link capacitors. It shows faster switching transition and less overshoot voltage compared to a module using an identical package but without capacitors. Active power cycling and passive temperature cycling are carried out for package reliability characterization and comparisons are made with commercial Si and SiC power modules. Scanning acoustic microscopy images and thermal structure functions are presented to quantify the effects of package degradation. The results demonstrate that the SiC modules with embedded capacitors have similar reliability performance to commercial modules and that the reliability is not adversely affected by the presence of the decoupling capacitors

Pipelined analog-to-digital conversion using current-mode reference shifting

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica e de ComputadoresPipeline Analog-to-digital converters (ADCs) are the most popular architecture for high-speed medium-to-high resolution applications. A fundamental, but often unreferenced building block of pipeline ADCs are the reference voltage circuits. They are required to maintain a stable reference with low output impedance to drive large internal switched capacitor loads quickly. Achieving this usually leads to a scheme that consumes a large portion of the overall power and area. A review of the literature shows that the required stable reference can be achieved with either on-chip buffering or with large off-chip decoupling capacitors. On-chip buffering is ideal for system integration but requires a high speed buffer with high power dissipation. The use of a reference with off-chip decoupling results in significant power savings but increases the pads of chip, the count of external components and the overall system cost. Moreover the amount of ringing on the internal reference voltage caused by the series inductance of the package makes this solution not viable for high speed ADCs. To address this challenge, a pipeline ADC employing a multiplying digital-to-analog converter (MDAC) with current-mode reference shifting is presented. Consequently, no reference voltages and, therefore, no voltage buffers are necessary. The bias currents are generated on-chip by a reference current generator that dissipates low power. The proposed ADC is designed in a 65 nm CMOS technology and operates at sampling rates ranging from 10 to 80 MS/s. At 40 MS/s the ADC dissipates 10.8 mW from a 1.2 V power supply and achieves an SNDR of 57.2 dB and a THD of -68 dB, corresponding to an ENOB of 9.2 bit. The corresponding figure of merit is 460 fJ/step

Power-efficient Circuit Architectures for Receivers Leveraging Nanoscale CMOS

Cellular and mobile communication markets, together with CMOS technology scaling, have made complex systems-on-chip integrated circuits (ICs) ubiquitous. Moving towards the internet of things that aims to extend this further requires ultra-low power and efficient radio communication that continues to take advantage of nanoscale CMOS processes. At the heart of this lie orthogonal challenges in both system and circuit architectures of current day technology. By enabling transceivers at center frequencies ranging in several tens of GHz, modern CMOS processes support bandwidths of up to several GHz. However, conventional narrowband architectures cannot directly translate or trade-off these speeds to lower power consumption. Pulse-radio UWB (PR-UWB), a fundamentally different system of communication enables this trade-off by bit-level duty-cycling i.e., power-gating and has emerged as an alternative to conventional narrowband systems to achieve better energy efficiency. However, system-level challenges in the implementation of transceiver synchronization and duty-cycling have remained an open challenge to realize the ultra-low power numbers that PR-UWB promises. Orthogonally, as CMOS scaling continues, approaching 28nm and 14nm in production digital processes, the key transistor characteristics have rapidly changed. Changes in supply voltage, intrinsic gain and switching speeds have rendered conventional analog circuit design techniques obsolete, since they do not scale well with the digital backend engines that dictate scaling. Consequently, circuit architectures that employ time-domain processing and leverage the faster switching speeds have become attractive. However, they are fundamentally limited by their inability to support linear domain-to-domain conversion and hence, have remained un-suited to high-performance applications. Addressing these requirements in different dimensions, two pulse-radio UWB receiver and a continuous-time filter silicon prototypes are presented in this work. The receiver prototypes focus on system level innovation while the filter serves as a demonstration vehicle for novel circuit architectures developed in this work. The PR-UWB receiver prototypes are implemented in a 65nm LP CMOS technology and are fully integrated solutions. The first receiver prototype is a compact UWB receiver front end operating at 4.85GHz that is aggressively duty-cycled. It occupies an active area of only 0.4 mm², thanks to the use of few inductors and RF G_m-C filters and incorporates an automatic-threshold-recovery-based demodulator for digitization. The prototype achieves a sensitivity of -88dBm at a data rate of 1Mbps (for a BER of 10^-3), while achieving the lowest energy consumption gradient (dP/df_data=450pJ/bit) amongst other receivers operating in the lower UWB band, for the same sensitivity. However, this prototype is limited by idle-time power consumption (e.g., bias) and lacks synchronization capability. A fully self-duty-cycled and synchronized UWB pulse-radio receiver SoC targeted at low-data-rate communication is presented as the second prototype. The proposed architecture builds on the automatic-threshold-recovery-based demodulator to achieve synchronization using an all-digital clock and data recovery loop. The SoC synchronizes with the incoming pulse stream from the transmitter and duty-cycles itself. The SoC prototype achieves a -79.5dBm, 1Mbps-normalized sensitivity for a >5X improvement over the state of the art in power consumption (375pJ/bit), thanks to aggressive signal path and bias circuit duty-cycling. The SoC is fully integrated to achieve RF-in to bit-out operation and can interface with off-chip, low speed digital components. Finally, switched-mode signal processing, a signal processing paradigm that enables the design of highly linear, power-efficient feedback amplifiers is presented. A 0.6V continuous-time filter prototype that demonstrates the advantages of this technique is presented in a 65nm GP CMOS process. The filter draws 26.2mW from the supply while operating at a full-scale that is 73% of the V_dd, a bandwidth of 70MHz and a peak signal-to-noise-and-distortion ratio (SNDR) of 55.8dB. This represents a 2-fold improvement in full-scale and a 10-fold improvement in the bandwidth over state-of-the-art filter implementations, while demonstrating excellent linearity and signal-to-noise ratio. To sum up, innovations spanning both system and circuit architectures that leverage the speeds of nanoscale CMOS processes to enable power-efficient solutions to next-generation wireless receivers are presented in this work

A 5 Gb/s Radiation Tolerant Laser Driver

A laser driver for data transmission at 5 Gb/s has been developed as a part of the Giga Bit Transceiver (GBT) project. The Giga Bit Laser Driver (GBLD) targets High Energy Physics (HEP) applications for which radiation tolerance is mandatory. The GBLD ASIC can drive both VCSELs and some types of edge emitting lasers. It is essentially composed of two drivers capable of sinking up to 12 mA each from the load at a maximum data rate of 5 Gb/s, and of a current sink for the laser bias current. The laser driver include also pre-emphasis and duty cycle control capabilities

Polymer Dipoles Relaxation and Potential Energy (New Simulation Model)

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ULTRA-THIN ON-CHIP ALD LIPON AS SOLID-STATE ELECTROLYTE FOR HIGH ENERGY AND HIGH FREQUENCY CAPACITOR APPLICATIONS

Liquid electrolytes dominate the supercapacitor market due to their high ionic conductivity leading to high energy and power density metrics. However, with the increase in demand for portable and implantable consumer electronics, all solid-state supercapacitor systems with high safety are an attractive option from both application perspectives and their similar charge storage mechanism. For solid state ionic capacitors, there remains significant room for innovation to increase the ionic conductivity and capacitor architecture to enhance the performance of these devices. Nano-structuring along with advanced manufacturing techniques such as atomic layer deposition (ALD) are powerful tools to augment the performance metrics of these all-solid-state capacitors that can compete with state-of-the-art liquid electrolyte-based supercapacitors. This dissertation has two primary objectives; 1) Study the behavior of polymorphs of ALD LiPON as a capacitor material and 2) Enhance the performance metrics using advanced materials and 3D nanostructuring for improved energy storage and high-frequency applications.In this work, ALD LiPON-based solid state capacitors are fabricated with a gold current collector to study the behavior of the solid electrolyte. LiPON shows a dual energy storage behavior, in low frequency (<10 kHz), LiPON shows an ionic behavior with electric double layer type energy storage, beyond this frequency, LiPON shows an electrostatic behavior with a dielectric constant of 14. The capacitor stack's thin film structure and dual frequency behavior allow for extended frequency operation of these capacitors (100 Hz to 2000 MHz). Next, LiPON's energy storage metrics are enhanced by pseudocapacitive energy storage behavior and increased surface area using ALD oxy-TiN. Finally, new fabrication techniques and ALD recipes are developed and optimized for integration into 3D templates. For fabrication of these capacitors, the material's chemistry is analyzed, and ALD techniques are developed for the deposition of electrode/electrolyte materials and current collectors into the 3D nanostructures. The intermixing during the ALD processes are studied to understand the behavior and reliability of these thin films. This work highlights LiPON characteristics as a capacitor material for high-energy and high-frequency applications. Though incomplete, we discuss progress towards the development of all ALD solid-state 3D supercapacitors that can compete against state-of-the-art capacitors available in the market