Effect of Temperature on Cu-doped p-ZnTe Thin-Films

In this paper we study the effect of temperature in 150 (±5) and 80 (±5) nm p-ZnTe thin- films immersed in 60 mgCu(NO3)2-3H2O/150 ml (H2O) for 1 minute, and heated at 200 and 300 °C for 30 minutes. Active layers were deposited by pulsed-laser deposition (PLD) at room temperature. Electrical parameters in un-doped films were around 108  ?109 ? and these values decreased to ~ 103 ? when the films were immersed in a Cu solution. The Cu-doped samples heated at 300 °C showed a completely homogeneous doping. X-ray diffraction (XRD) patterns showed the orthorhombic structure at 200 and 300 °C

Atomic Layer Deposition of ZnO on Multi-walled Carbon Nanotubes and Its Use for Synthesis of CNT-ZnO Heterostructures.

In this article, direct coating of ZnO on PECVD-grown multi-walled carbon nanotubes (MWCNTs) is achieved using atomic layer deposition (ALD). Transmission electron microscopy investigation shows that the deposited ZnO shell is continuous and uniform, in contrast to the previously reported particle morphology. The ZnO layer has a good crystalline quality as indicated by Raman and photoluminescence (PL) measurements. We also show that such ZnO layer can be used as seed layer for subsequent hydrothermal growth of ZnO nanorods, resulting in branched CNT-inorganic hybrid nanostructures. Potentially, this method can also apply to the fabrication of ZnO-based hybrid nanostructures on other carbon nanomaterials.RIGHTS : This article is licensed under the BioMed Central licence at http://www.biomedcentral.com/about/license which is similar to the 'Creative Commons Attribution Licence'. In brief you may : copy, distribute, and display the work; make derivative works; or make commercial use of the work - under the following conditions: the original author must be given credit; for any reuse or distribution, it must be made clear to others what the license terms of this work are

Analysis on Band Layer Design and J-V characteristics of Zinc Oxide Based Junction Field Effect Transistor

This paper presents the band gap design and J-V characteristic curve of Zinc Oxide (ZnO) based on Junction Field Effect Transistor (JFET). The physical properties for analysis of semiconductor field effect transistor play a vital role in semiconductor measurements to obtain the high-performance devices. The main objective of this research is to design and analyse the band diagram design of semiconductor materials which are used for high performance junction field effect transistor. In this paper, the fundamental theory of semiconductors, the electrical properties analysis and bandgap design of materials for junction field effect transistor are described. Firstly, the energy bandgaps are performed based on the existing mathematical equations and the required parameters depending on the specified semiconductor material. Secondly, the J-V characteristic curves of semiconductor material are discussed in this paper. In order to achieve the current-voltage characteristic for specific junction field effect transistor, numerical values of each parameter which are included in analysis are defined and then these resultant values are predicted for the performance of junction field effect transistors. The computerized analyses have also mentioned in this paper

Gain-tunable complementary common-source amplifier based on a flexible hybrid thin-film transistor technology

In this letter, we report a flexible complementary common-source (CS) amplifier comprising one p-type spray-coated single walled carbon nanotube and one n-type sputtered InGaZnO4 thin-film transistor (TFT). Bottom-gate TFTs were realized on a free-standing flexible polyimide foil using a maximum process temperature of 150 °C. The resulting CS amplifier operates at 10 V supply voltage and exhibits a gain bandwidth product of 60 kHz. Thanks to the use of a p-type TFT acting as a tunable current source load, the amplifier gain can be programmed from 3.5 V/V up to 27.2 V/V (28.7 dB). To the best of our knowledge, this is the highest gain ever obtained for a flexible single-stage CS amplifiers

Atomic Layer Deposition of ZnO on Multi-walled Carbon Nanotubes and Its Use for Synthesis of CNT–ZnO Heterostructures

In this article, direct coating of ZnO on PECVD-grown multi-walled carbon nanotubes (MWCNTs) is achieved using atomic layer deposition (ALD). Transmission electron microscopy investigation shows that the deposited ZnO shell is continuous and uniform, in contrast to the previously reported particle morphology. The ZnO layer has a good crystalline quality as indicated by Raman and photoluminescence (PL) measurements. We also show that such ZnO layer can be used as seed layer for subsequent hydrothermal growth of ZnO nanorods, resulting in branched CNT–inorganic hybrid nanostructures. Potentially, this method can also apply to the fabrication of ZnO-based hybrid nanostructures on other carbon nanomaterials

Radiation sensitive MOSFETs irradiated with various positive gate biases

The RADiation sensitive metal-oxide-semiconductor field-effect-transistors (RADFETs) were irradiated with gamma rays up to absorbed dose of 110 Gy(H2O). The results of threshold voltage, VT, during irradiation with various positive gate biases showed the increase in VT with gate bias. The threshold voltage shift, ΔVT, during irradiation was fitted very well. The contributions of both the fixed traps (FTs) and switching traps (STs) during radiation on ΔVT were analyzed. The results show the significantly higher contribution of FTs than STs. A function that describes the dependence of threshold voltage shift and its components on gate bias was proposed, which fitted the experimental values very well. The annealing at the room temperature without gate bias of irradiated RADFETs was investigated. The recovery of threshold voltage, known as fading, slightly increase with the gate bias applied during radiation. The ΔVT shows the same changes as the threshold voltage component due to fixed states, ΔVft, while there is no change in the threshold voltage component due to switching traps, ΔVst

Radiation sensitive MOSFETs irradiated with various positive gate biases

This work was supported in part by the European Union's Horizon 2020 research and innovation programme under grant agreement No. 857558, and the Ministry of Education, Science and Technological Development of the Republic of Serbia, under the project No. 43011.The RADiation sensitive metal-oxide-semiconductor field-effect-transistors (RADFETs) were irradiated with gamma rays up to absorbed dose of 110 Gy(H2O). The results of threshold voltage, V-T , during irradiation with various positive gate biases showed the increase in V-T with gate bias. The threshold voltage shift, Delta V-T , during irradiation was fitted very well. The contributions of both the fixed traps (FTs) and switching traps (STs) during radiation on Delta V-T were analyzed. The results show the significantly higher contribution of FTs than STs. A function that describes the dependence of threshold voltage shift and its components on gate bias was proposed, which fitted the experimental values very well. The annealing at the room temperature without gate bias of irradiated RADFETs was investigated. The recovery of threshold voltage, known as fading, slightly increase with the gate bias applied during radiation. The Delta V-T shows the same changes as the threshold voltage component due to fixed states, Delta V-ft , while there is no change in the threshold voltage component due to switching traps, Delta V-st .European Union's Horizon 2020 research and innovation programme 857558Ministry of Education, Science & Technological Development, Serbia 4301

Thin Film Electronics Based on ZnO and ZnO/MgZnO Heterojunctions.

The ZnO TFT (Thin Film Transistor) has demonstrated improved electron mobility over entrenched, a-Si, technologies and is receiving considerable attention as an alternative TFT technology due to high transparency in the visible region and potential for flexible electronics on conformal substrates. This work studied the material properties of ZnO thin films deposited by pulsed laser deposition, provided a qualitative discussion of TFT operation, applied the buried-channel approach to enhance channel mobility, and demonstrated a complementary logic inverter circuit based on an n-channel ZnO TFT and a p-channel ZnTe TFT. The material study in this work focused on optimal deposition conditions needed to realize low-resistivity ZnO thin films. Various techniques were used to illustrate the effect of decreasing polycrystalline ZnO grain size on carrier mobility and background carrier concentration as a function of thickness. Building on these results, discussion of TFT operating principles concentrated on explaining its dependence on carrier concentration and active-channel thickness. The resulting performance of surface-channel ZnO TFTs demonstrated saturation mobility of μSAT = 1.8cm2/Vs, current on/off ratio of ION/IOFF > 109, and off current of IOFF=10pA. A buried-channel approach to suppress the effect of electron trapping on carrier transport by isolating the ZnO active channel was presented. Quantum confined structures, such as quantum wells, enhance speed of electronic devices due to carrier confinement. Quantum wells based on the ZnO/MgxZn1-xO (x≤0.3) material system have been grown on c-plane sapphire substrates. Luminescent properties characterized by low-temperature photoluminescence revealed quantum confinement with a systematic blueshift as a function of decreasing ZnO well width in the range from 3nm to 10nm. An enhancement in saturation mobility of 3.9cm2/V-s was achieved by utilizing the ZnO/MgZnO heterojunctions to fabricate a buried-channel TFT. Finally, incorporation of a ZnTe TFT, exhibiting relatively high hole mobility (~5cm2/Vs), and ZnO TFTs in a complementary logic inverter circuit demonstrated reasonable transfer characteristics. Inverter behavior is demonstrated, with a high output voltage of VOH >14V and low output voltage of VOL5 at Vin=6V.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/75806/1/wbowen_1.pd

Memristive behavior in a junctionless flash memory cell

We report charge storage based memristive operation of a junctionless thin film flash memory cell when it is operated as a two terminal device by grounding the gate. Unlike memristors based on nanoionics, the presented device mode, which we refer to as the flashristor mode, potentially allows greater control over the memristive properties, allowing rational design. The mode is demonstrated using a depletion type n-channel ZnO transistor grown by atomic layer deposition (ALD), with HfO2 as the tunnel dielectric, Al2O3 as the control dielectric, and non-stoichiometric silicon nitride as the charge storage layer. The device exhibits the pinched hysteresis of a memristor and in the unoptimized device, Roff/Ron ratios of about 3 are presented with low operating voltages below 5 V. A simplified model predicts Roff/Ron ratios can be improved significantly by adjusting the native threshold voltage of the devices. The repeatability of the resistive switching is excellent and devices exhibit 106s retention time, which can, in principle, be improved by engineering the gate stack and storage layer properties. The flashristor mode can find use in analog information processing applications, such as neuromorphic computing, where well-behaving and highly repeatable memristive properties are desirable. © 2015 AIP Publishing LLC