Overcoming the Challenges for Multichip Integration: A Wireless Interconnect Approach

The physical limitations in the area, power density, and yield restrict the scalability of the single-chip multicore system to a relatively small number of cores. Instead of having a large chip, aggregating multiple smaller chips can overcome these physical limitations. Combining multiple dies can be done either by stacking vertically or by placing side-by-side on the same substrate within a single package. However, in order to be widely accepted, both multichip integration techniques need to overcome significant challenges. In the horizontally integrated multichip system, traditional inter-chip I/O does not scale well with technology scaling due to limitations of the pitch. Moreover, to transfer data between cores or memory components from one chip to another, state-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the target chip over a wireline interconnect fabric. This multi-hop communication increases energy consumption while decreasing data bandwidth in a multichip system. On the other hand, in vertically integrated multichip system, the high power density resulting from the placement of computational components on top of each other aggravates the thermal issues of the chip leading to degraded performance and reduced reliability. Liquid cooling through microfluidic channels can provide cooling capabilities required for effective management of chip temperatures in vertical integration. However, to reduce the mechanical stresses and at the same time, to ensure temperature uniformity and adequate cooling competencies, the height and width of the microchannels need to be increased. This limits the area available to route Through-Silicon-Vias (TSVs) across the cooling layers and make the co-existence and co-design of TSVs and microchannels extreamly challenging. Research in recent years has demonstrated that on-chip and off-chip wireless interconnects are capable of establishing radio communications within as well as between multiple chips. The primary goal of this dissertation is to propose design principals targeting both horizontally and vertically integrated multichip system to provide high bandwidth, low latency, and energy efficient data communication by utilizing mm-wave wireless interconnects. The proposed solution has two parts: the first part proposes design methodology of a seamless hybrid wired and wireless interconnection network for the horizontally integrated multichip system to enable direct chip-to-chip communication between internal cores. Whereas the second part proposes a Wireless Network-on-Chip (WiNoC) architecture for the vertically integrated multichip system to realize data communication across interlayer microfluidic coolers eliminating the need to place and route signal TSVs through the cooling layers. The integration of wireless interconnect will significantly reduce the complexity of the co-design of TSV based interconnects and microchannel based interlayer cooling. Finally, this dissertation presents a combined trade-off evaluation of such wireless integration system in both horizontal and vertical sense and provides future directions for the design of the multichip system

An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links

As semiconductor technologies continues to scale, more and more cores are being integrated on the same multicore chip. This increase in complexity poses the challenge of efficient data transfer between these cores. Several on-chip network architectures are proposed to improve the design flexibility and communication efficiency of such multicore chips. However, in a larger system consisting of several multicore chips across a board or in a System-in-Package (SiP), the performance is limited by the communication among and within these chips. Such systems, most commonly found within computing modules in typical data center nodes or server racks, are in dire need of an efficient interconnection architecture. Conventional interchip communication using wireline links involve routing the data from the internal cores to the peripheral I/O ports, travelling over the interchip channels to the destination chip, and finally getting routed from the I/O to the internal cores there. This multihop communication increases latency and energy consumption while decreasing data bandwidth in a multichip system. Furthermore, the intrachip and interchip communication architectures are separately designed to maximize design flexibility. Jointly designing them could, however, improve the communication efficiency significantly and yield better solutions. Previous attempts at this include an all-photonic approach that provides a unified inter/intra-chip optical network, based on recent progress in nano-photonic technologies. Works on wireless inter-chip interconnects successfully yielded better results than their wired counterparts, but their scopes were limited to establishing a single wireless connection between two chips rather than a communication architecture for a system as a whole. In this thesis, the design of a seamless hybrid wired and wireless interconnection network for multichip systems in a package is proposed. The design utilizes on-chip wireless transceivers with dimensions spanning up to tens of centimeters. It manages to seamlessly bind both intrachip and interchip communication architectures and enables direct chip-to-chip communication between the internal cores. It is shown through cycle accurate simulations that the proposed design increases the bandwidth and reduces the energy consumption when compared to the state-of-the-art wireline I/O based multichip communications

Design and simulation of a multichip module

Electronic packaging has undergone basic changes in the last few years to keep up with an ever increasing demand for speed and miniaturization. Multichip Modules (MCM) represent a class of advanced packaging technologies. This thesis examines various MCM technologies and their relative advantages and disadvantages. Further, the design process for an MCM is presented in detail. The physical design and simulation for the performance ( electrical and thermal) is also detailed. A design example ties together all the issues that are relevant to the design of an MCM

Advanced information processing system for advanced launch system: Hardware technology survey and projections

The major goals of this effort are as follows: (1) to examine technology insertion options to optimize Advanced Information Processing System (AIPS) performance in the Advanced Launch System (ALS) environment; (2) to examine the AIPS concepts to ensure that valuable new technologies are not excluded from the AIPS/ALS implementations; (3) to examine advanced microprocessors applicable to AIPS/ALS, (4) to examine radiation hardening technologies applicable to AIPS/ALS; (5) to reach conclusions on AIPS hardware building blocks implementation technologies; and (6) reach conclusions on appropriate architectural improvements. The hardware building blocks are the Fault-Tolerant Processor, the Input/Output Sequencers (IOS), and the Intercomputer Interface Sequencers (ICIS)

Supply chain control: Trade-offs and system requirements

The official published version can be accessed from the link below.A paper describes the underlying forces which drive change in manufacturing enterprises and supply chains. It sets out the complexities in modern capitalism and global economics and illustrates the trade-offs that can be made. IT systems which are required to assist improvements to both customer service and enterprise manufacturing performance are explained, alluding to the special case for the semiconductor industry. Arguments are presented showing how the new tools being developed with the ESPRIT project 20544, X-CITTIC, will satisfy the control needs for a virtual enterprise. This paper describes the underlying forces which drive change in manufacturing enterprises and supply chains. It sets out the complexities in modem capitalism and global economics and illustrates the trade-offs that can be made. IT systems which are required to assist improvements to both customer service and enterprise manufacturing performance are explained alluding to the special case for the semiconductor industry. Finally it shows how the new tools being developed with the ESPRIT project 20544, XCITTIC, will satisfy the control needs for a virtual enterprise

Packaging Design of IGBT Power Module Using Novel Switching Cells

Parasitic inductance in power modules generates voltage spikes and current ringing during switching which cause extra stress in power electronic devices, increase electromagnetic interference (EMI), and degrade the performance of the power converter system. As newer power devices have faster switching speeds and higher power ratings, the effect of the parasitic inductance of the power module is more pronounced. This dissertation proposes a novel packaging method for power electronics modules based on the concepts of novel switching cells: P-cell and N-cell. It can reduce the stray inductance in the current commutation path in a phase-leg module and hence improve the switching behavior. Taking an insulated gate bipolar transistor (IGBT) as an example, two phase-leg modules, specifically a conventional module and a P-cell and N-cell based module were designed. Using Ansoft Q3D Extractor, electromagnetic simulation was carried out to extract the stray inductance from the two modules. An ABB 1200 V / 75 A IGBT model and a diode model were built for simulation study. Circuit parasitics were extracted and modeled. Switching behavior with different package parasitics was studied based on the Saber simulation. Two prototype phase-leg modules were fabricated. The parasitics were measured using a precision impedance analyzer. The measurement results agree with the simulation very well. A double pulse tester was built in laboratory. Several approaches were used to reduce the circuit and measuring parasitics. From the switching characteristics of the two modules, it was verified that the larger stray inductance in the layout causes higher voltage overshoot during turn off, which in turn increases the turn off losses. Multichip (two in parallel) IGBT modules applying novel switching cells was also designed. The parasitics were extracted and compared to a conventional design. The overall loop inductance was reduced in the proposed module. However, the mismatch of the paralleled branches was larger

Stepwise Design Methodology and Heterogeneous Integration Routine of Air-Cooled SiC Inverter for Electric Vehicle

Carrying on SiC devices, the air-cooled inverter of the electric vehicle (EV) can eliminate the traditional complicated liquid-cooling system in order to obtain a light and compact performance of the powertrain, which is considered as the trend of next-generation EV. However, the air-cooled SiC inverter lacks strategic design methodology and heterogeneous integration routine for critical components. In this article, a stepwise design methodology is proposed for the air-cooled SiC inverter in the power module, dc-link capacitor, and heat sink levels. In the power module level, an electrical-thermal-mechanical multiphysics model is proposed. The multidimension stress distribution principles in a six-in-one SiC power module are demonstrated. An improved power module is presented and confirmed by using the observed multiphysics design principles. In the dc-link capacitor level, ripple modeling of the inverter and capacitor are created. Considering the tradeoffs among ripple voltage, ripple current, and cost, optimal strategies to determine the material and minimize the capacitance of the dc-link capacitor are proposed. In the heat sink level, thermal resistance of air-cooled heat sink is modeled. Structure and material properties of the heat sink are optimally designed by using a comprehensive electro-thermal analysis. Based on the optimal design results, the prototypes of the customized SiC power module and heterogeneously integrated air-cooled inverter are fabricated. Experimental results are presented to demonstrate the feasibility of the designed and manufactured air-cooled SiC inverter.Ministry of Education (MOE)Nanyang Technological UniversityThis work was supported in part by the National Natural Science Foundation of China under Grant 51607016, in part by the National Key Research and Development Program of China under Grant 2017YFB0102303, and in part by the Singapore ACRF Tier 1 Grant RG 85/18. The work of X. Zhang was supported by the NTU Startup Grant (SCOPES)

The Development and Packaging of a High-Density, Three-Phase, Silicon Carbide (SiC) Motor Drive

Technology advances within the power electronics field are resulting in systems characterized by higher operating efficiencies, reduced footprint, minimal form factor, and decreasing mass. In particular, these attributes and characteristics are being inserted into numerous consumer applications, such as light-emitting diode lighting, compact fluorescent lighting, smart phones, and tablet PCs, to industrial applications that include hybrid, electric, and plug-in electric vehicles and more electric aircraft. To achieve the increase in energy efficiency and significant reduction in size and mass of these systems, power semiconductor device manufacturers are developing silicon carbide (SiC) semiconductor technology. In this dissertation, the author discusses the design, development, packaging, and fabrication of the world\u27s first multichip power module (MCPM) that integrates SiC power transistors with silicon-on-insulator (SOI) integrated circuits. The fabricated MCPM prototype is a 4 kW, three-phase inverter that operates at temperatures in excess of 250 °C. The integration of high-temperature metal-oxide semiconductor (HTMOS) SOI bare die control components with SiC power JFET bare die into a single compact module are presented in this work. The high-temperature operation of SiC switches allows for increased power density over silicon electronics by an order of magnitude, leading to highly miniaturized power converters. This dissertation is organized into a compilation of publications written by the author over the course of his Ph.D. work. The work presented throughout these publications covers the challenges associated with power electronics miniaturization and packaging including high-power density, high-temperature, and high-efficiency operation of the power electronic system under study