371 research outputs found
Dynamic Security-aware Routing for Zone-based data Protection in Multi-Processor System-on-Chips
In this work, we propose a NoC which enforces the
encapsulation of sensitive traffic inside the asymmetrical security
zones while using minimal and non-minimal paths. The NoC
routes guarantee that the sensitive traffic is communicated only
through the trusted nodes which belong to the security zone.
As the shape of the zones may change during operation, the
sensitive traffic must be routed through low-risk paths. We test
our proposal and we show that our solution can be an efficient
and scalable alternative for enforce the data protection inside the
MPSoC
Heuristics for Routing and Spiral Run-time Task Mapping in NoC-based Heterogeneous MPSOCs
This paper describes a new Spiral Dynamic Task Mapping heuristic for mapping
applications onto NoC-based Heterogeneous MPSoC. The heuristic proposed in this
paper attempts to map the tasks of an applications that are most related to
each other in spiral manner and to find the best possible path load that
minimizes the communication overhead. In this context, we have realized a
simulation environment for experimental evaluations to map applications with
varying number of tasks onto an 8x8 NoC-based Heterogeneous MPSoCs platform, we
demonstrate that the new mapping heuristics with the new modified dijkstra
routing algorithm proposed are capable of reducing the total execution time and
energy consumption of applications when compared to state-of the-art run-time
mapping heuristics reported in the literature
On-Line Dependability Enhancement of Multiprocessor SoCs by Resource Management
This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. First, the NoC dependability is functionally verified via embedded software. Then the Xentium processor tiles are periodically verified via on-line self-testing techniques, by using a new IIP Dependability Manager. Based on the Dependability Manager results, faulty tiles are electronically excluded and replaced by fault-free spare tiles via on-line resource management. This integrated approach enables fast electronic fault detection/diagnosis and repair, and hence a high system availability. The dependability application runs in parallel with the actual application, resulting in a very dependable system. All parts have been verified by simulation
Mapeo estĂĄtico y dinĂĄmico de tareas en sistemas multiprocesador, basados en redes en circuito integrado
RESUMEN: Las redes en circuito integrado (NoC) representan un importante paradigma de uso creciente para los sistemas multiprocesador en circuito integrado (MPSoC), debido a su flexibilidad y escalabilidad. Las estrategias de tolerancia a fallos han venido adquiriendo importancia, a medida que los procesos de manufactura incursionan en dimensiones por debajo del micrĂłmetro y la complejidad de los diseños aumenta. Este artĂculo describe un algoritmo de aprendizaje incremental basado en poblaciĂłn (PBIL), orientado a optimizar el proceso de mapeo en tiempo de diseño, asĂ como a encontrar soluciones de mapeo Ăłptimas en tiempo de ejecuciĂłn, para hacer frente a fallos de Ășnico nodo en la red. En ambos casos, los objetivos de optimizaciĂłn corresponden al tiempo de ejecuciĂłn de las aplicaciones y al ancho de banda pico que aparece en la red. Las simulaciones se basaron en un algoritmo de ruteo XY determinĂstico, operando sobre una topologĂa de malla 2D para la NoC. Los resultados obtenidos son prometedores. El algoritmo propuesto exhibe un desempeño superior a otras tĂ©cnicas reportadas cuando el tamaño del problema aumenta.ABSTARCT: Due to its scalability and flexibility, Network-on-Chip (NoC) is a growing and promising communication paradigm for Multiprocessor System-on-Chip (MPSoC) design. As the manufacturing process scales down to the deep submicron domain and the complexity of the system increases, fault-tolerant design strategies are gaining increased relevance. This paper exhibits the use of a Population-Based Incremental Learning (PBIL) algorithm aimed at finding the best mapping solutions at design time, as well as to finding the optimal
remapping solution, in presence of single-node failures on the NoC. The optimization objectives in both cases are the application completion time and the network's peak bandwidth. A deterministic XY routing algorithm was used in order to simulate the traffic conditions in the network which has a 2D mesh topology. Obtained results are promising. The proposed algorithm exhibits a better performance, when compared with other reported approaches, as the problem size increases
Energy-Aware Scheduling of Conditional Task Graphs on NoC-Based MPSoCs
We investigate the problem of scheduling a set of tasks with individual deadlines and conditional precedence constraints on a heterogeneous Network on Chip (NoC)-based Multi-Processor System-on-Chip (MPSoC) such that the total expected energy consumption of all the tasks is minimized, and propose a novel approach. Our approach consists of a scheduling heuristic for constructing a single unified schedule for all the tasks and assigning a frequency to each task and each communication assuming continuous frequencies, an Integer Linear Programming (ILP)-based algorithm and a polynomial time heuristic for assigning discrete frequencies and voltages to tasks and communications. We have performed experiments on 16 synthetic and 4 real-world benchmarks. The experimental results show that compared to the state-of-the-art approach, our approach using the ILP-based algorithm and our approach using the polynomial-time heuristic achieve average improvements of 31% and 20%, respectively, in terms of energy reduction
A survey on scheduling and mapping techniques in 3D Network-on-chip
Network-on-Chips (NoCs) have been widely employed in the design of
multiprocessor system-on-chips (MPSoCs) as a scalable communication solution.
NoCs enable communications between on-chip Intellectual Property (IP) cores and
allow those cores to achieve higher performance by outsourcing their
communication tasks. Mapping and Scheduling methodologies are key elements in
assigning application tasks, allocating the tasks to the IPs, and organising
communication among them to achieve some specified objectives. The goal of this
paper is to present a detailed state-of-the-art of research in the field of
mapping and scheduling of applications on 3D NoC, classifying the works based
on several dimensions and giving some potential research directions
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