PTS and AICF Combined PAPR Reduction Techniques in Multi-Antenna OFDM Systems

A high PAPR value is one of important weaknesses in OFDM systems. Several reduction techniques are applied to reduce PAPR including partial transmit sequence (PTS) as well as clipping and filtering (CF). Adaptive iterative clipping and filtering is a development of iterative clipping and filtering techniques. In this paper, a combination of Partial transmits sequence and adaptive iterative clipping filtering (PTS-AICF) techniques on multi-antenna OFDM transmitters was carried out. The simulation results showed that combined technique application had a better performance than non-combined technique (PTS), either for two or four antennas, and also for different sub block numbers. Performance was also influenced by iterations number on AICF section, the more iterations were used, the better the reduction technique performance was because it produced smaller PAPR 0 value

Laboratorios de simulación de un sistema de multiplexación por división de frecuencias ortogonales

Este proyecto se encarga de la simulación de un sistema de multiplexación por división de frecuencias ortogonales mediante la programación a través del software Vissim Comm® de cada una de sus etapas, para luego evaluar su desempeño, calculando y midiendo (en la simulación) su tasa de error de bits VER, con su respectiva curva BER vs SNR. Así mismo se elaboran una serie de laboratorios para comprender el funcionamiento de los sistemas de frecuencias ortogonales y determinar cada una de sus propiedades como: eficiencia espectral, inmunidad a la multitrayectoria, entre otros. A través de un laboratorio se compara un sistema que aplica IFFT a varios símbolos y sistemas de múltiples portadoras ortogonales, y se establece que ambos son equivalentes.Incluye bibliografí

Design and Implementation of MIMO OFDM IEEE802.11n Receiver Blocks on Heterogeneous Multicore Architecture

In this thesis, the performance of a heterogeneous multicore platform in terms of technical capability is evaluated. Therefore, the choice of architecture in general can be based on a set of diverse applications. Selected applications can be parallel or serial in nature. Applications evaluation are often based on various performance metrics including the resource utilization and execution time. The wireless communication systems are expanded to accelerate their functions execution in both software and hardware. The embedded systems which involve several types of communication systems perform a large number of computations which require short execution time and minimized power consumption. Also, there is a growing demand for application-specific accelerators aiding general-purpose. One feasible way is to use heterogeneous multi-core platforms. Furthermore, many application-specific accelerators are loosely connected with each other. In this study, the implementation of Multiple-Input Multiple-Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) receiver is evaluated by applying a Heterogeneous Multicore Architecture (HMA). The MIMO OFDM receiver is composed of computationally intensive and general-purpose processing tasks and can serve maximum coverage for evaluation of the HMA. The receiver blocks are designed by crafting template-based Coarse-grained Reconfigurable Array (CGRA) devices. In this case study, four streams (antennas) are proposed in order to process the data over CGRAs simultaneously. HMA nodes will be reconfigured at run-time in different blocks of the receiver. In this experimental work, according to the performance of each CGRA, the collective performance of the entire platform as well as NoC traffic is recorded considering the number of clock cycles and also several high-level performance criteria. The implementation of OFDM receiver scaled CGRAs to various dimensions. The data can also be exchanged between diverse nodes on the NoC structure by utilizing direct memory access (DMA) devices independently

Cell-Free Multi-User Massive MIMO Under Channel Non-Reciprocity

In Cell-Free (CF) Massive multiple-input multiple-output (MIMO), a large number of access points (AP) are geographically distributed over the coverage area, and jointly serve a smaller number of users on the same time/frequency resources. In this thesis, we study the impact of non-reciprocal channels (NRC) and imperfect channel state information (CSI) on Cell-Free massive MIMO systems performance. As non-reciprocity sources, we consider transceiver frequency response mismatches and mutual-coupling mismatches in uplink and downlink analogue processing chains. We study both single-antenna and multi-antenna AP configurations, and in this last case, we also include non-reciprocal mutual coupling in addition to transceiver frequency responses. We present a novel non-reciprocal channel model based on experimental results from massive MIMO reciprocity calibration tests. Previous models consider that channel non-reciprocity characteristics are fast-varying like random variables; conversely, we consider a model where non-reciprocity values change substantially slower in time, as demonstrated in experimental results. Besides, we derive closed-form analytical expressions of capacity lower bounds for zero-forcing and conjugate beamforming schemes. The conclusion is that non-reciprocal channels can be a limiting factor for Cell-Free systems performance; nevertheless, only AP mismatches impact on performance while UE mismatches do not affect performance. Furthermore, only phase non-reciprocity degrades MRT performance, whereas both phase and amplitude non-reciprocity degrade ZF performance. Therefore, calibration requirements may dispense with amplitude compensation when APs use MRT scheme, and prioritise phase over amplitude compensation when APs use ZF scheme. Mutual coupling considerately affects both MRT and ZF precoders, but ZF to a greater extent. Hence, calibration procedures should always try to compensate for mutual coupling non-reciprocity

Design and Implementation of Software Defined Radio Accelerators Using An Adaptive Coarse-Grain Reconfigurable Array and Processor Software

Over the past few decades, the development of wireless communication systems in both hardware and software calls for the speed-up in the execution of the involved functions. Moreover, in embedded systems which are including different types of communication systems, a large number of computations yet with short execution time are needed while power consumption is required to be minimized. There is an increasing demand to use application-specific accelerators assisting general-purpose RISC processors. This thesis focuses on designing the application-specific accelerators for Orthogonal Frequency Division Multiplexing (OFDM) IEEE 802.11a receiver blocks using CREMA (Coarse-grain REconfigurable array with Mapping Adaptiveness). At first, some of the common techniques used in OFDM receivers are presented. Then, the basic structure of COFFEE RISC processor as the main implementation platform is described. In addition, the definition of different reconfigurable architectures has been discussed. The experimental part of this research work covers the design and implementation of three different application-specific accelerators for OFDM receiver blocks. The accelerators work particularly for COFFEE RISC core firmly integrated with a Direct Memory Access (DMA) device. The performance of the accelerators is evaluated in terms of the number of clock cycles, resource utilization and synthesis frequency on an Altera Stratix-IV Field Programmable Gate Array (FPGA) device. It is observed that the designed accelerators give speed-up of 4.8× to 18.6× in comparison with COFFEE RISC processor software

An enhanced multicarrier modulation system for mobile communications

PhD ThesisThe recent revolution in mobile communications and the increased demand on more efficient transmission systems influence the research to enhance and invent new modulation techniques. Orthogonal frequency division multiplexing with offset quadrature amplitude modulation (OFDM/OQAM) is one of the multicarrier modulations techniques that overcomes some of the weaknesses of the conventional OFDM in term of bandwidth and power efficiencies. This thesis presents a novel multicarrier modulation scheme with improved performance in mobile communications context. Initially, the theoretical principles behind OFDM and OFDM/OQAM are discussed and the advantages of OFDM/OQAM over OFDM are highlighted. The time-frequency localization of pulse shapes is examined over different types of pulses. The effect of the localization and the pulse choice on OFDM/OQAM performance is demonstrated. The first contribution is introducing a new variant of multicarrier modulation system based on the integration of the Walsh-Hadamard transform with the OFDM/OQAM modulator. The full analytical transmission model of the system is derived over flat fading and frequency selective channels. Next, because of the critical requirement of low implementation complexity in mobile systems, a new fast algorithm transform is developed to reduce the implementation complexity of the system. The introduced fast algorithm has demonstrated a remarkable 60 percent decrease in the hardware requirement compared to the cascaded configuration. Although, the problem of high peak to average power ratio (PAPR) is one of the main drawbacks that associated with most multicarrier modulation techniques, the new system achieved lower values compared to the conventional systems. Subsequently, three new algorithms to reduce PAPR named Walsh overlapped selective mapping (WOSLM) for a high PAPR reduction, simplified selective mapping (SSLM) for a very low implementation complexity and Walsh partial transmit sequence (WPTS), are developed. Finally, in order to assess the reliability of the presented system in this thesis at imperfect environments, the performance of the system is investigated in the presence of high power amplifier, channel estimation errors, and carrier frequency offset (CFO). Two channel estimations algorithms named enhanced pair of pilots (EPOP) and averaged enhanced pair of pilots (AEPOP), and one CFO estimator technique called frequency domain (FD) CFO estimator, are suggested to provide reliable performance.Ministry of Higher Education and Scientific Research (MOHSR) of Ira

Power and Energy Aware Heterogeneous Computing Platform

During the last decade, wireless technologies have experienced significant development, most notably in the form of mobile cellular radio evolution from GSM to UMTS/HSPA and thereon to Long-Term Evolution (LTE) for increasing the capacity and speed of wireless data networks. Considering the real-time constraints of the new wireless standards and their demands for parallel processing, reconfigurable architectures and in particular, multicore platforms are part of the most successful platforms due to providing high computational parallelism and throughput. In addition to that, by moving toward Internet-of-Things (IoT), the number of wireless sensors and IP-based high throughput network routers is growing at a rapid pace. Despite all the progression in IoT, due to power and energy consumption, a single chip platform for providing multiple communication standards and a large processing bandwidth is still missing.The strong demand for performing different sets of operations by the embedded systems and increasing the computational performance has led to the use of heterogeneous multicore architectures with the help of accelerators for computationally-intensive data-parallel tasks acting as coprocessors. Currently, highly heterogeneous systems are the most power-area efficient solution for performing complex signal processing systems. Additionally, the importance of IoT has increased significantly the need for heterogeneous and reconfigurable platforms.On the other hand, subsequent to the breakdown of the Dennardian scaling and due to the enormous heat dissipation, the performance of a single chip was obstructed by the utilization wall since all cores cannot be clocked at their maximum operating frequency. Therefore, a thermal melt-down might be happened as a result of high instantaneous power dissipation. In this context, a large fraction of the chip, which is switched-off (Dark) or operated at a very low frequency (Dim) is called Dark Silicon. The Dark Silicon issue is a constraint for the performance of computers, especially when the up-coming IoT scenario will demand a very high performance level with high energy efficiency. Among the suggested solution to combat the problem of Dark-Silicon, the use of application-specific accelerators and in particular Coarse-Grained Reconfigurable Arrays (CGRAs) are the main motivation of this thesis work.This thesis deals with design and implementation of Software Defined Radio (SDR) as well as High Efficiency Video Coding (HEVC) application-specific accelerators for computationally intensive kernels and data-parallel tasks. One of the most important data transmission schemes in SDR due to its ability of providing high data rates is Orthogonal Frequency Division Multiplexing (OFDM). This research work focuses on the evaluation of Heterogeneous Accelerator-Rich Platform (HARP) by implementing OFDM receiver blocks as designs for proof-of-concept. The HARP template allows the designer to instantiate a heterogeneous reconfigurable platform with a very large amount of custom-tailored computational resources while delivering a high performance in terms of many high-level metrics. The availability of this platform lays an excellent foundation to investigate techniques and methods to replace the Dark or Dim part of chip with high-performance silicon dissipating very low power and energy. Furthermore, this research work is also addressing the power and energy issues of the embedded computing systems by tailoring the HARP for self-aware and energy-aware computing models. In this context, the instantaneous power dissipation and therefore the heat dissipation of HARP are mitigated on FPGA/ASIC by using Dynamic Voltage and Frequency Scaling (DVFS) to minimize the dark/dim part of the chip. Upgraded HARP for self-aware and energy-aware computing can be utilized as an energy-efficient general-purpose transceiver platform that is cognitive to many radio standards and can provide high throughput while consuming as little energy as possible. The evaluation of HARP has shown promising results, which makes it a suitable platform for avoiding Dark Silicon in embedded computing platforms and also for diverse needs of IoT communications.In this thesis, the author designed the blocks of OFDM receiver by crafting templatebased CGRA devices and then attached them to HARP’s Network-on-Chip (NoC) nodes. The performance of application-specific accelerators generated from templatebased CGRAs, the performance of the entire platform subsequent to integrating the CGRA nodes on HARP and the NoC traffic are recorded in terms of several highlevel performance metrics. In evaluating HARP on FPGA prototype, it delivers a performance of 0.012 GOPS/mW. Because of the scalability and regularity in HARP, the author considered its value as architectural constant. In addition to showing the gain and the benefits of maximizing the number of reconfigurable processing resources on a platform in comparison to the scaled performance of several state-of-the-art platforms, HARP’s architectural constant ensures application-independent figure of merit. HARP is further evaluated by implementing various sizes of Discrete Cosine transform (DCT) and Discrete Sine Transform (DST) dedicated for HEVC standard, which showed its ability to sustain Full HD 1080p format at 30 fps on FPGA. The author also integrated self-aware computing model in HARP to mitigate the power dissipation of an OFDM receiver. In the case of FPGA implementation, the total power dissipation of the platform showed 16.8% reduction due to employing the Feedback Control System (FCS) technique with Dynamic Frequency Scaling (DFS). Furthermore, by moving to ASIC technology and scaling both frequency and voltage simultaneously, significant dynamic power reduction (up to 82.98%) was achieved, which proved the DFS/DVFS techniques as one step forward to mitigate the Dark Silicon issue