One Modification of the Alternating Step Generator

Report published in the Proceedings of the National Conference on "Education and Research in the Information Society", Plovdiv, May, 2019In this paper, we propose a research on the modified alternating step generator implementation based on feedback with carry shift registers. The scheme is proposed by Schneier. We calculated the period of the derivative algorithm. The key gamma is statistically tested with NIST test suite. The result of the analysis shows that the output data are such a random physical phenomena generated.Association for the Development of the Information Society, Institute of Mathematics and Informatics Bulgarian Academy of Sciences, Plovdiv University "Paisii Hilendarski

Hardware Mechanisms for Efficient Memory System Security

The security of a computer system hinges on the trustworthiness of the operating system and the hardware, as applications rely on them to protect code and data. As a result, multiple protections for safeguarding the hardware and OS from attacks are being continuously proposed and deployed. These defenses, however, are far from ideal as they only provide partial protection, require complex hardware and software stacks, or incur high overheads. This dissertation presents hardware mechanisms for efficiently providing strong protections against an array of attacks on the memory hardware and the operating system’s code and data. In the first part of this dissertation, we analyze and optimize protections targeted at defending memory hardware from physical attacks. We begin by showing that, contrary to popular belief, current DDR3 and DDR4 memory systems that employ memory scrambling are still susceptible to cold boot attacks (where the DRAM is frozen to give it sufficient retention time and is then re-read by an attacker after reboot to extract sensitive data). We then describe how memory scramblers in modern memory controllers can be transparently replaced by strong stream ciphers without impacting performance. We also demonstrate how the large storage overheads associated with authenticated memory encryption schemes (which enable tamper-proof storage in off-chip memories) can be reduced by leveraging compact integer encodings and error-correcting code (ECC) DRAMs – without forgoing the error detection and correction capabilities of ECC DRAMs. The second part of this dissertation presents Neverland: a low-overhead, hardware-assisted, memory protection scheme that safeguards the operating system from rootkits and kernel-mode malware. Once the system is done booting, Neverland’s hardware takes away the operating system’s ability to overwrite certain configuration registers, as well as portions of its own physical address space that contain kernel code and security-critical data. Furthermore, it prohibits the CPU from fetching privileged code from any memory region lying outside the physical addresses assigned to the OS kernel and drivers. This combination of protections makes it extremely hard for an attacker to tamper with the kernel or introduce new privileged code into the system – even in the presence of software vulnerabilities. Neverland enables operating systems to reduce their attack surface without having to rely on complex integrity monitoring software or hardware. The hardware mechanisms we present in this dissertation provide building blocks for constructing a secure computing base while incurring lower overheads than existing protections.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147604/1/salessaf_1.pd

Synchronization for capacity -approaching coded communication systems

The dissertation concentrates on synchronization of capacity approaching error-correction codes that are deployed in noisy channels with very low signal-to-noise ratio (SNR). The major topics are symbol timing synchronization and frame synchronization.;Capacity-approaching error-correction codes, like turbo codes and low-density parity-check (LDPC) codes, are capable of reaching very low bit error rates and frame error rates in noisy channels by iterative decoding. To fully achieve the potential decoding capability of Turbo codes and LDPC codes, proper symbol timing synchronization, frame synchronization and channel state estimation are required. The dissertation proposes a joint estimator of symbol time delay and channel SNR for symbol timing recovery, and a maximum a posteriori (MAP) frame synchronizer for frame synchronization.;Symbol timing recovery is implemented by sampling and interpolation. The received signal is sampled multiple times per symbol period with unknown delay and unknown SNR. A joint estimator estimates the time delay and the SNR. The signal is rebuilt by interpolating available samples using estimated time delay. The intermediate decoding results enable decision-feedback estimation. The estimates of time delay and SNR are refined by iterative processing. This refinement improves the system performance significantly.;Usually the sampling rate is assumed to be a strict integer multiple of the symbol rate. However, in a practical system the local oscillators in the transmitter and the receiver may have random drifts. Therefore the sampling rate is no longer an exact multiple of the symbol rate, and the sampling time follows a random walk. This random walk may harm the system performance severely. The dissertation analyzes the effect of random time walks and proposes to mitigate the effect by overlapped sliding windows and iterative processing.;Frame synchronization is required to find the correct boundaries of codewords. MAP frame synchronization in the sense of minimizing the frame sync failure rate is investigated. The MAP frame synchronizer explores low-density parity-check attributes of the capacity-approaching codes. The accuracy of frame synchronization is adequate for considered coded systems to work reliably under very low SNR

An all-digital transmitter for pulsed ultra-wideband communication

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 91-96).Applications like sensor networks, medical monitoring, and asset tracking have led to a demand for energy-efficient and low-cost wireless transceivers. These types of applications typically require low effective data rates, thus providing an opportunity to employ simple modulation schemes and aggressive duty-cycling. Due to their inherently duty-cycled nature, pulse-based Ultra-Wideband (UWB) systems are amenable to low-power operation by shutting off circuitry during idle mode between pulses. Furthermore, the use of non-coherent UWB signaling greatly simplifies both transmitter and receiver implementations, offering additional energy savings. This thesis presents an all-digital transmitter designed for a non-coherent pulsed UWB system. By exploiting relaxed center frequency tolerances in non-coherent wideband communication, the transmitter synthesizes UWB pulses from an energy efficient, single-ended digital ring oscillator. Dual capacitively-coupled digital power amplifiers (PAs) are used in tandem to generate bipolar phase modulated pulses for spectral scrambling purposes. By maintaining opposite common modes at the output of these PAs during idle mode (i.e. when no pulses are being transmitted), low frequency turn-on and turn-off transients typically associated with single-ended digital circuits driving single-ended antennas are attenuated by up to 12dB. Furthermore, four level digital pulse shaping is employed to attenuate RF side lobes by up to 20dB. The resulting dual power amplifiers achieve FCC compliant operation in the 3.5, 4.0, and 4.5GHz IEEE 802.15.4a bands without the use of any off-chip filters or large passive components. The transmitter is fabricated in a 90nm CMOS process and requires a core area of 0.07mm2. The entirely digital architecture consumes zero static bias current, resulting in an energy efficiency of 17.5pJ/pulse at data rates up to 15.6Mbps.by Patrick Philip Mercier.S.M

Absence of barren plateaus in finite local-depth circuits with long-range entanglement

Ground state preparation is classically intractable for general Hamiltonians. On quantum devices, shallow parameterized circuits can be effectively trained to obtain short-range entangled states under the paradigm of variational quantum eigensolver, while deep circuits are generally untrainable due to the barren plateau phenomenon. In this Letter, we give a general lower bound on the variance of circuit gradients for arbitrary quantum circuits composed of local 2-designs. Based on our unified framework, we prove the absence of barren plateaus in training finite local-depth circuits for the ground states of local Hamiltonians. These circuits are allowed to be deep in the conventional definition of circuit depth so that they can generate long-range entanglement, but their local depths are finite, i.e., there is only a finite number of non-commuting gates acting on individual qubits. This fact suggests that long-range entangled ground states, such as topologically ordered states, are in general possible to be prepared efficiently on quantum devices via variational methods. We validate our analytical results with extensive numerical simulations and demonstrate the effectiveness of variational training using the generalized toric code model.Comment: 28 pages, 7 figure

A PCI Express board designed to interface with the electronic phase-2 upgrades of the ATLAS detectors at CERN

Nei prossimi 10 anni è in previsione un aggiornamento radicale dell'acceleratore LHC al CERN finalizzato al raggiungimento di più alti valori di luminosità istantanea (oltre \begin{math}5 \times 10^{34}cm^{-2}s^{-1}\end{math}) ed integrata (oltre un fattore 10 rispetto a quella attuale). Conseguentemente, anche i rilevatori degli esperimenti che lavorano al CERN, così come i loro sistemi di acquisizione dati, dovranno essere aggiornati per poter gestire un flusso notevolmente maggiore rispetto a quello utilizzato finora. Questa tesi tratta in particolare di una nuova scheda elettronica di lettura, progettata e testata nel laboratorio di elettronica del Dipartimento di Fisica ed Astronomia dell'Università di Bologna e nel laboratorio di elettronica della Sezione INFN (Istituto Nazionale di Fisica Nucleare) di Bologna. Le motivazioni che hanno indotto lo sviluppo della scheda prototipale sono molteplici. Un primo obiettivo da perseguire è stato quello di aggiornare la versione attuale delle schede elettroniche di acquisizione dati usate oggi nel Pixel Detector dell'esperimento ATLAS, visto che sono anch'esse sotto la responsabilità della sezione INFN di Bologna. Secondariamente, la scheda (nominata Pixel-ROD) è orientata a gestire le esigenze elettroniche che seguiranno l'upgrade di LHC durante la fase 2. La complessità del progetto e l'inerzia intrinseca di una vasta collaborazione come quella di ATLAS, hanno poi indotto lo sviluppo di questo progetto elettronico in largo anticipo rispetto al vero upgrade di fase 2 di LHC, previsto per il 2024. In questo modo saranno anche più facilmente eseguibili eventuali aggiornamenti tecnologici in corso d'opera, senza dover riprogettare da zero un sistema di acquisizione dati completo

Novel structures for high-speed delta-sigma data converters

As CMOS processes keep scaling down devices, the maximum operating frequencies of CMOS devices increase, and hence circuits can process very wide band signals. Moreover, the small physical dimensions of transistors allow the placing of many more blocks into a single chip, including highly accurate analog blocks and complicated digital blocks, which can process audio to communication data. Nowadays, wideband and low-power data converter is mandatory for mobile applications which need a bridge between analog and digital blocks. In this dissertation, low-power and wideband techniques are proposed. An embedded-adder quantizer with dynamic preamplifier is proposed to achieve power-efficient operation. Various double-sampling schemes are studied, and novel schemes are presented to achieve wideband operation without noise folding effect. To reduce timing delay and idle tones, a high speed DEM which alternates two sets of comparator references is proposed. Multi-cell architecture is studied to insure higher performance when the number of modulators increases. 0.18 um double-poly/4-metal CMOS process was used to implement a prototype IC. 20 MHz signal bandwidth was achieved with a 320 MHz sampling clock. The peak SNDR was 63 dB. The figure-of-merit FoM = P/(2*BW*2[superscript ENOB]) was 0.35 pJ/conversion, with a 16 mW power consumption. Measurement results show that the proposed design ideas are useful for low-power and wideband delta-sigma modulators which have low OSR. A second-order noise-coupled modulator with an embedded-zero optimization was proposed to reduce power consumption by eliminating some of the integrators. This architecture makes easier the implementation of the small feedback capacitors for high OSR modulators

NASA Tech Briefs Index, 1978

Approximately 601 announcements of new technology derived from the research and development activities of the National Aeronautics and Space Administration are presented. Emphasis is placed on information considered likely to be transferrable across industrial, regional, or disciplinary lines. Subject matter covered includes: electronic components and circuits; electron systems; physical sciences; materials; life sciences; mechanics; machinery; fabrication technology; and mathematics and information sciences

Brillouin Echoes for Advanced Distributed Sensing in Optical Fibres

Brillouin scattering is particularly efficient and attractive for the implementation of strain and temperature distributed sensing in optical fibres. Recently a trend has been observed that modern advanced applications require a substantial step towards better spatial resolution, while preserving temperature/strain precision over a long range. For this purpose the state of the art does not satisfy all these requirements. In this thesis we present a radically new approach named Brillouin Echoes distributed sensing (BEDS) that allows covering these requirements. In the first part, we propose an updated configuration of the classical existing Brillouin sensor for time domain analysis allowing drastic noise reduction. Then we investigate the limitations (due to non-linear effects) of the classical Brillouin sensor in terms of long distance range measurements. The identified nonlinear effects are pump depletion due to SBS itself, self-phase modulation (SPM), modulation instability (MI), which occurs only in fibres presenting an anomalous dispersion at the pump wavelength and Raman scattering (RS). We propose the modeling of the pump depletion effect to obtain analytical expressions that are useful for the proper design of a BOTDA sensor and for the determination of a very small depletion. The model confirmed by experimental measurements is informative on the conditions maximizing the depletion effect; therefore a standard configuration can be defined to test the value of the depletion in the set-up. Furthermore, we demonstrate that SPM-induced spectral broadening can have a significant effect on the measured effective gain linewidth. Modeling and experiments have undoubtedly demonstrated that the effective gain linewidth can easily experience a two-fold increase in standard conditions when the pulse intensity profile is Gaussian. We showed that the problem can be practically circumvented by using a clean rectangular pulse with very sharp rising and falling edges. The theoretical and experimental analysis of the undesirable effects of MI and forward RS in distributed BOTDA sensors systems gives a simplified expression to predict the critical power for a given distance range. MI turns out to be the dominant nonlinear limitation since it shows the lowest critical power, but it is less critical since it can be avoided to a wide extent by using the fibre in the normal dispersion spectral region such as a DSF in the C-band. On the other hand Raman scattering can be avoided only by limiting the optical pump power and therefore is the ultimate nonlinear limitation in a distributed sensing system. Under similar conditions RS shows a critical power ∼5 times larger than MI. In the second part, we present the new approach Brillouin echo distributed sensing (BEDS) which has proved to be a powerful solution to realize sub-metric spatial resolutions in Brillouin distributed measurements. We have demonstrated both theoretically and experimentally that an optimized configuration is reached when the optical wave is π-phase shifted. The experimental tests have shown a spatial resolution down to 5 cm, with a clear margin for further improvement down to a real centimetric spatial resolution. This optimized configuration produce the best contrast independently of the pulse intensity, with a factor 2 of improvement compared to other techniques based on the same approach (dark pulse, bright pulse). This extends the dynamic range by 3 dB, which corresponds in standard loss conditions to a 5 km extension of the sensing range. An analytical developed model has proved to be an excellent tool not only for optimizing the pumping scheme but also in post-processing the measured data. Finally the potentialities of BEDS technology provide solutions in real contexts. Using the BEDS technology in landslide monitoring at laboratory scale, for the first time it became possible to observe the failure propagation in laboratory scale with an accurate precision. Furthermore, using BEDS we have proposed and demonstrated the possibility of mapping geometrical structure fluctuations along a photonic crystal fibre (PCF). Both long- and short-scale longitudinal fluctuations in the Brillouin frequency shift have been identify and quantify. Observation of Brillouin linewidth broadening in PCF fibre through distributed measurement of the Brillouin gain spectrum using BEDS has allowed fundamental understanding of SBS in PCF fibre and in their design in view of applications to optical-strain/temperature sensing

Error Behaviour In Optical Networks

Optical fibre communications are now widely used in many applications, including local area computer networks. I postulate that many future optical LANs will be required to operate with limited optical power budgets for a variety of reasons, including increased system complexity and link speed, low cost components and minimal increases in transmit power. Some developers will wish to run links with reduced power budget margins, and the received data in these systems will be more susceptible to errors than has been the case previously. The errors observed in optical systems are investigated using the particular case of Gigabit Ethernet on fibre as an example. Gigabit Ethernet is one of three popular optical local area interconnects which use 8B/10B line coding, along with Fibre Channel and Infiniband, and is widely deployed. This line encoding is also used by packet switched optical LANs currently under development. A probabilistic analysis follows the effects of a single channel error in a frame, through the line coding scheme and the MAC layer frame error detection mechanisms. Empirical data is used to enhance this original analysis, making it directly relevant to deployed systems. Experiments using Gigabit Ethernet on fibre with reduced power levels at the receiver to simulate the effect of limited power margins are described. It is found that channel bit error rate and packet loss rate have only a weakly deterministic relationship, due to interactions between a number of non-uniform error characteristics at various network sub-layers. Some data payloads suffer from high bit error rates and low packet loss rates, compared to others with lower bit error rates and yet higher packet losses. Experiments using real Internet traffic contribute to the development of a novel model linking packet loss, the payload damage rate, and channel bit error rate. The observed error behaviours at various points in the physical and data link layers are detailed. These include data-dependent channel errors; this error hot- spotting is in contrast to the failure modes observed in a copper-based system. It is also found that both multiple channel errors within a single code-group, and multiple error instances within a frame, occur more frequently than might be expected. The overall effects of these error characteristics on the ability of cyclic redundancy checks (CRCs) to detect errors, and on the performance of higher layers in the network, is considered. This dissertation contributes to the discussion of layer interactions, which may lead to un-foreseen performance issues at higher levels of the network stack, and extends it by considering the physical and data link layers for a common form of optical link. The increased risk of errors in future optical networks, and my findings for 8B/10B encoded optical links, demonstrate the need for a cross-layer understanding of error characteristics in such systems. The development of these new networks should take error performance into account in light of the particular requirements of the application in question.The UK Engineering and Physical Sciences Research Council and Marconi Corporation supported my work financially through an Industrial CASE studentship