Low-temperature amorphous oxide semiconductors for thin-film transistors and memristors: physical insights and applications

While amorphous oxides semiconductors (AOS), namely InGaZnO (IGZO), have found market application in the display industry, their disruptive properties permit to envisage for more advanced concepts such as System-on-Panel (SoP) in which AOS devices could be used for addressing (and readout) of sensors and displays, for communication, and even for memory as oxide memristors are candidates for the next-generation memories. This work concerns the application of AOS for these applications considering the low thermal budgets (< 180 °C) required for flexible, low cost and alternative substrates. For maintaining low driving voltages, a sputtered multicomponent/multi-layered high-κ dielectric (Ta2O5+SiO2) was developed for low temperature IGZO TFTs which permitted high performance without sacrificing reliability and stability. Devices’ performance under temperature was investigated and the bias and temperature dependent mobility was modelled and included in TCAD simulation. Even for IGZO compositions yielding very high thermal activation, circuit topologies for counteracting both this and the bias stress effect were suggested. Channel length scaling of the devices was investigated, showing that operation for radio frequency identification (RFID) can be achieved without significant performance deterioration from short channel effects, which are attenuated by the high-κ dielectric, as is shown in TCAD simulation. The applicability of these devices in SoP is then exemplified by suggesting a large area flexible radiation sensing system with on-chip clock-generation, sensor matrix addressing and signal read-out, performed by the IGZO TFTs. Application for paper electronics was also shown, in which TCAD simulation was used to investigate on the unconventional floating gate structure. AOS memristors are also presented, with two distinct operation modes that could be envisaged for data storage or for synaptic applications. Employing typical TFT methodologies and materials, these are ease to integrate in oxide SoP architectures

Interpretation and Regulation of Electronic Defects in IGZO TFTs Through Materials & Processes

The recent rise in the market for consumer electronics has fueled extensive research in the field of display. Thin-Film Transistors (TFTs) are used as active matrix switching devices for flat panel displays such as LCD and OLED. The following investigation involves an amorphous metal-oxide semiconductor that has the potential for improved performance over current technology, while maintaining high manufacturability. Indium-Gallium-Zinc-Oxide (IGZO) is a semiconductor material which is at the onset of commercialization. The low-temperature large-area deposition compatibility of IGZO makes it an attractive technology from a manufacturing standpoint, with an electron mobility that is 10 times higher than current amorphous silicon technology. The stability of IGZO TFTs continues to be a challenge due to the presence of defect states and problems associated with interface passivation. The goal of this dissertation is to further the understanding of the role of defect states in IGZO, and investigate materials and processes needed to regulate defects to the level at which the associated influence on device operation is controlled. The relationships between processes associated with IGZO TFT operation including IGZO sputter deposition, annealing conditions and back-channel passivation are established through process experimentation, materials analysis, electrical characterization, and modeling of electronic properties and transistor behavior. Each of these components has been essential in formulating and testing several hypotheses on the mechanisms involved, and directing efforts towards achieving the goal. Key accomplishments and quantified results are summarized as follows: • XPS analysis identified differences in oxygen vacancies in samples before and after oxidizing ambient annealing at 400 °C, showing a drop in relative integrated area of the O 1s peak from 32% to 19%, which experimentally translates to over a thousand fold decrease in the channel free electron concentration. • Transport behavior at cryogenic temperatures identified variable range hopping as the electron transport mechanism at temperature below 130 K, whereas at temperature greater than 130 K, the current vs temperature response followed an Arrhenius relationship consistent with extended state transport. • Refinement of an IGZO material model for TCAD simulation, which consists of oxygen vacancy donors providing an integrated space charge concentration NVO = +5e15 cm-3, and acceptor-like band-tail states with a total integrated ionized concentration of NTA = -2e18 cm-3. An intrinsic electron mobility was established to be Un = 12.7 cm2/V∙s. • A SPICE-compatible 2D on-state operation model for IGZO TFTs has been developed which includes the integration of drain-impressed deionization of band-tail states and results in a 2D modification of free channel charge. The model provides an exceptional match to measured data and TCAD simulation, with model parameters for channel mobility (Uch = 12 cm2/V∙s) and threshold voltage (VT = 0.14 V) having a close match to TCAD analogs. • TCAD material and device models for bottom-gate and double-gate TFT configurations have been developed which depict the role of defect states on device operation, as well as provide insight and support of a presented hypothesis on DIBL like device behavior associated with back-channel interface trap inhomogeneity. This phenomenon has been named Trap Associated Barrier Lowering (TABL). • A process integration scheme has been developed that includes IGZO back-channel passivation with PECVD SiO2, furnace annealing in O2 at 400 °C, and a thin capping layer of alumina deposited via atomic layer deposition. This process supports device stability when subjected to negative and positive bias stress conditions, and thermal stability up to 140 °C. It also enables TFT operation at short channel lengths (Leff ~ 3 µm) with steep subthreshold characteristics (SS ~ 120 mV/dec). The details of these contributions in the interpretation and regulation of electronic defect states in IGZO TFTs is presented, along with the support of device characteristics that are among the best reported in the literature. Additional material on a complementary technology which utilizes flash-lamp annealing of amorphous silicon will also be described. Flash-Lamp Annealed Polycrystalline Silicon (FLAPS) has realized n-channel and p-channel TFTs with promising results, and may provide an option for future applications with the highest performance demands. IGZO is rapidly emerging as the candidate to replace a-Si:H and address the performance needs of display products produced by large panel manufacturing

Indium-Gallium-Zinc Oxide Thin-Film Transistors for Active-Matrix Flat-Panel Displays

Amorphous oxide semiconductors (AOSs) including amorphous InGaZnO (a-IGZO) areexpected to be used as the thin-film semiconducting materials for TFTs in the next-generation ultra-high definition (UHD) active-matrix flat-panel displays (AM-FPDs). a-IGZO TFTs satisfy almost all the requirements for organic light-emitting-diode displays (OLEDs), large and fast liquid crystal displays (LCDs) as well as three-dimensional (3D) displays, which cannot be satisfied using conventional amorphous silicon (a-Si) or polysilicon (poly-Si) TFTs. In particular, a-IGZO TFTs satisfy two significant requirements of the backplane technology: high field-effect mobility and large-area uniformity.In this work, a robust process for fabrication of bottom-gate and top-gate a-IGZO TFTs is presented. An analytical drain current model for a-IGZO TFTs is proposed and its validation is demonstrated through experimental results. The instability mechanisms in a-IGZO TFTs under high current stress is investigated through low-frequency noise measurements. For the first time, the effect of engineered glass surface on the performance and reliability of bottom-gate a-IGZO TFTs is reported. The effect of source and drain metal contacts on electrical properties of a-IGZO TFTs including their effective channel lengths is studied. In particular, a-IGZO TFTs with Molybdenum versus Titanium source and drain electrodes are investigated. Finally, the potential of aluminum substrates for use in flexible display applications is demonstrated by fabrication of high performance a-IGZO TFTs on aluminum substrates and investigation of their stability under high current electrical stress as well as tensile and compressive strain

A Second-Order ΣΔ ADC using sputtered IGZO TFTs with multilayer dielectric

This dissertation combines materials science and electronics engineering to implement, for the first time, a 2nd-order ∑∆ ADC using oxide TFTs. The transistors employ a sputtered IGZO semiconductor and an optimizeddielectric layer, based on mixtures of sputtered Ta2O5and SiO2. These dielectrics are studied in multilayer configurations, being the best results achieved for 7 layers: IG7.5 MV/cm, while keeping κ>10, yielding a major improvement over Ta2O5single-layer. After annealing at 200 °C, TFTs with these dielectrics exhibit μSAT≈13 cm2/Vs, On/Off≈107and S≈0.2 V/dec. An a-Si:H TFT RPI model is adapted to simulate these devices with good fitting to experimental data. Concerning circuits, the ∑∆ architecture is naturally selected to deal with device mismatch. After design optimization, ADC simulations achieve SNDR≈57 dB, DR≈65 dB and power dissipation, approximately, of 22 mW (VDD=10 V), which are above the current state-of-the-art for competing thinfilm technologies, such as organics or even LTPS. Mask layouts are currently under verification to enable successful circuit fabrication in the next months.This work is a major step towards the design of complex multifunctional electronic systems with oxide TFT technology, being integrated in ongoing EU-funded and FCT-funded research projects at CENIMAT and UNINOVA

Circuit Design and Compact Modeling in Printed Electronics Based on Inorganic Materials

Die gedruckte Elektronik ist ein im Vergleich zur konventionellen Siliziumtechnologie junges Forschungsgebiet. Die Idee hinter der gedruckten Elektronik ist es elektronische Bauteile wie Widerstände, Kapazitäten, Solarzellen, Dioden und Transistoren mit gängigen Druckmethoden herzustellen. Dabei ist es möglich die elektronischen Bauteile auf unbiegsamen Substrate, wie Glas oder Silizium, als auch auf biegsamen Substrate, wie Papier und Folie, zu drucken. Aufgrund des Druckprozesses, sind die Herstellungskosten gering, da drucken ein additiver Prozess ist und somit teure Masken obsolet sind. In einem Feldeffekttransistor, wird der Halbleiter zwischen zwei Elektroden (Drain- und Source) gedruckt. Die Drain- und Source-Elektroden werden dabei durch einen Vakuum- oder Druckprozess abgeschieden und strukturiert. Der halbleitende Kanal wird durch einen Dielektrikum von der Gate-Elektrode isoliert. Auch für das Dielektrikum und die Gate-Elektrode sind ein Vakuum- oder Druckprozess denkbar. Standardmäßig finden organische Materialien Einsatz in der gedruckten Elektronik. Leider weisen organische Halbleiter, in einem Feldeffekttransistor, nur eine geringe Ladungsträgerbeweglichkeit ($\leq 1$ cm$^2$(Vs)$^{-1}$) auf. Die niedrige Ladungsträgerbeweglichkeit führt zu einer geringen Ladungsträgerdichte im Halbleiter und als Resultat zu geringen Stromdichten. Auch sind größtenteils nur p-leitende Halbleiter für den Einsatz in Schaltungen vorhanden, weswegen die meisten Schaltungen nur p-leitende Feldeffekttransistoren besitzen. Ein weiterer Nachteil der organischen Elektronik ist, dass die eingesetzten Dielektrika mit dem Halbleiter eine mangelhafte Grenzfläche bildet. Deshalb sind Versorgungsspannungen in Bereich von 5 V keine Seltenheit. Eine interessante Alternative zu organischen Halbleitern sind Materialien die der Kategorie der Oxide zugeordnet sind. Zum Beispiel in Indiumoxid (In$_{2}$O$_{3}$) ist eine Ladungsträerbeweglichkeit um die 100 cm$^2$(Vs)$^{-1}$ messbar. Leider sind durch Oxide realisierte p-leitende Feldeffekttransistoren sehr selten, weshalb die meisten Schaltungen auf n-leitenden Feldeffekttransistoren basieren. Ein weiterer Nachteil von Metalloxidhalbleitern is das hohe Glühtemperaturen (\sim 400 \, ^\circC) benötigt werden um die richtige Kristallstruktur zu erzielen. Durch den Einsatz eines Elektrolyten, anstatt eines Dielektrikum, werden die benötigten hohen Versorgungsspannungen auf 1 V reduziert. Der Grund für die Reduzierung der Versorgungsspannung liegt in der hohen Kapazität ($\sim 5 \, \mu$F(cm)$^{-1}$), die sich zwischen der Gate-Elektrode und dem Kanal ausbildet. Die optimale Grenzfläche zwischen der Gate-Elektrode und dem Elektrolyten sowie als auch zwischen dem Elektrolyten und dem Kanal, wo sich eine Helmholtz-Doppelschicht ausbildet, ist der Grund für die hohe Kapazität. In dieser Arbeit, werden die Vorteile der hohen Ladungsträgerbeweglichkeit, resultierend von einem Indiumoxid-Kanal, und der niedrigen Versorgungsspannungen, durch den Einsatz eines Elektrolyten als Isolator, in einem gedruckten Transistor kombiniert. Daher ist das Ziel zunächst Transistoren basierend auf einem Elektrolyten und Indiumoxid-Kanal zu charakterisieren und zu modellieren. Auch werden Möglichkeiten zum Schaltungsentwurf mit der hier vorgestellten Transistortechnologie ausgearbeitet. Der Schaltungsentwurf wird anhand mikroelektronischen Zellen und Ringoszillator-Strukturen verifiziert. Wichtig für den Schaltungsentwurf sind Modelle die fähig sind die elektrischen Eigenschaften eines Transistors abzubilden. Dabei muss die simulierte Kurve Stetigkeit und Kontinuität aufweisen um Konvergenzprobleme während der Simulation zu verhindern. Zur Modellierung der elektrischen Eigenschaften und Ströme der Transistoren wird ein Modell basierend auf den Curtice-Modell entwickelt. Der Bereich über der Schwellwertspannung wird daher durch das Curtice-Modell abgebildet und der Bereich unter der Schwellspannung durch ein aus Siliziumtransistoren bekanntes Standard-Modell beschrieben. Kontinuität und Stetigkeit wird durch eine Interpolation zwischen den beiden Transistormodellen gewährleistet. Ein Verglich zwischen gemessenen und simulierten Daten zeigt das das Modell die hier vorgestellte Transistortechnologie sehr gut abbilden kann. Das entwickelte Transistormodel wird zur unterstützung des Schaltungsentwurf in einem Prozesskit (PDK) integriert. Dadurch ist das Verhalten einer Schaltung durch Simulation vorhersehbar. In der Simulation können auch der Einfluss der Umwelt, z.B. Luftfeuchtigkeit, auf die Transistoren analysiert werden. In der digitalen Schaltungstechnik wird ein p-leitender Feldeffekttransistor verwendet um ein Eingangssignal hochzusetzen, während um ein Signal runterzusetzen, ein n-leitender Feldeffekttransistor von Vorteil ist. Da p-leitende Oxide selten und unzuverlässig sind, wird der p-leitende Feldeffekttransistor durch einen Widerstand (Transistor-Widerstand-Logik (TRL)) oder einen n-leitenden Feldeffekttransistor (Transistor-Transistor-Logik (TTL)) ersetzt. Ein Inverter in TRL weist bei einer Versorgungsspannung von 1 V einen Verstärkungsfaktor von ungefähr -5 auf und eine Signalverzögerung von 0.9 ms. Die Oszillatorfrequenz im entsprechend Ringoszillator beträgt 296 Hz. Weitere Logikgatter (NAND, NOR und XOR) sind ebenfalls realisierbar mit TRL-Entwürfe. In TTL wird der p-leitende Feldeffekttransistor durch einen n-leitenden Verarmungstyps Feldeffekttransistor ersetzt. Die in der TTL entworfene Logikgatter verhalten sich identisch zu den TTR-Zellen aber die Frequenz vom Ringoszillator steigt bis in den unteren kHz-Bereich an. In TTL ist es ebenfalls möglich die Verlustleistung um einen Faktor von 6 zu reduzieren

Sputtered Zn-Sn-O based thin-film transistors: Optimization and circuit simulation

The development of amorphous oxide semiconductors (AOS) has been accelerated with their application in thin-film transistors (TFTs) for transparent and flexible displays. Among the many AOS available, zinc tin oxide (ZTO) represents a promising material due to its enhanced chemical and physical properties and the abundance of its elements in nature results in low price, compared to IGZO, and favours its widespread use in mass technology production. In this work, ZTO thin films deposited by sputtering under different oxygen, hydrogen and RF power conditions were investigated. The study focus on their morphology, structure and optical behaviour and on their implementation as active channel layers in TFTs. Great device performance was obtained when deposited at a power of 160 W, in a 10% of oxygen partial pressure and 1% of hydrogen, at a 2.3 mTorr pressure. After an annealing temperature of 180 oC, mobility of 9.1 cm2 V-1s-1, subthreshold slope of 0.29 Vdec-1 and turn-on voltage of -2.0 V were achieved, using a sputtered multilayer dielectric based on Ta2O5-SiO2. The measured output and transfer a-ZTO TFT characteristics were modeled in an artificial neural network (ANNs) empirical model with very good accuracy. The model was used in the Cadence Spectre to simulate three logic gates at DC and transient analysis: inverter, NAND and NOR, with logic levels preserved up to 10 kHz

Amorphous oxide semiconductors in circuit applications

The focus of this thesis is the investigation of thin-film transistors (TFTs) based on amorphous oxide semiconductors (AOSs) in two circuit applications. To date, circuits implemented with AOS-based TFTs have been primarily enhancement-enhancement inverters, ring oscillators based on these inverters operating at peak frequencies up to ~400 kHz, and two-transistor one-capacitor pixel driving circuits for use with organic light-emitting diodes (OLEDS). The first application investigated herein is AC/DC rectification using two circuit configurations based on staggered bottom-gate TFTs employing indium gallium oxide (IGO) as the active channel layer; a traditional full bridge rectifier with diode-tied transistors and a cross-tied full-wave rectifier are demonstrated, which is analogous to what has been reported previously using p-type organic TFTs. Both circuit configurations are found to operate successfully up to at least 20 MHz; this is believed to be the highest reported operating frequency to date for circuits based on amorphous oxide semiconductors. Output voltages at one megahertz are 9 V and ~10.5 V, respectively, when driven with a differential 7.07 Vrms sine wave. This performance is superior to that of previously reported organic-based rectifiers. The second AOS-based TFT circuit application investigated is an enhancement-depletion (E-D) inverter based on heterogeneous channel materials. Simulation results using models based on a depletion-mode indium zinc oxide (IZO) TFT and an enhancement-mode IGO TFT result in a gain of ~15. Gains of other oxide-based inverters have been limited to less than 2; the large gain of the E-D inverter makes it well suited for digital logic applications. Deposition parameters for the IGO and IZO active layers are optimized to match the models used in simulation by fabricating TFTs on thermally oxidized silicon and patterned via shadow masks. Integrated IGO-based TFTs exhibit a similar turn-on voltage and decreased mobility compared to the shadow masked TFTs. However, the integrated IZO-based TFTs fabricated to date are found to be conductive and exhibit no gate modulation. Due to the conductive nature of the load, the fabricated E-D inverter shows no significant output voltage variation. This discrepancy in performance between the integrated and shadow-masked IZO devices is attributed to processing complications

용액 공정 인듐갈륨징크 산화물 박막트랜지스터의 뒷 채널 전위 및 드바이 길이를 고려한 결함구조밀도와 신뢰성에 대한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 홍용택.차세대 디스플레이 응용의 핵심 소자로 비정질 산화물 반도체 박막 트랜지스터에 대한 관심이 높아지고 있다. 특히 비정질 인듐갈륨징크 산화물 반도체는 전하 이동도와 같은 전기적 특성, 균일도, 그리고 공정 온도 등에서 한계에 있는 기존의 실리콘 기반 박막트랜지스터를 대체할 수 있을 것으로 기대되고 있다. 이와 더불어 공정 비용 감소를 위해 용액 공정 기반의 인듐갈륨징크 산화물 반도체 박막 트랜지스터에 대한 연구도 많이 이루어지고 있다. 하지만 보다 많은 응용을 위해서는 용액 공정 기반 인듐갈륨징크 산화물 박막트랜지스터의 물리적인 성질에 대한 연구가 필요한 상황이다. 또한 뒷 채널 영역의 소자 특성에 대한 영향은 인듐갈륨징크 산화물 반도체 박막트랜지스터의 분석에서 간과되어 왔으나, 채널 특성이 뒷 채널 영역 특성의 영향을 받을 정도로 반도체 층이 얇을 때에는 뒷 채널 영역의 영향을 무시할 수 없게 된다. 일반적으로 용액 공정 인듐갈륨징크 산화물 반도체 박막트랜지스터의 경우 10~20 nm의 매우 얇은 반도체 층을 갖기 때문에 소자를 분석할 때에 뒷 채널 표면의 영향은 고려되어야 한다. 본 학위 논문에서는 용액 공정 인듐갈륨징크 산화물 박막트랜지스터의 결함구조밀도와 같은 소자 물리적 특성과 정전압 스트레스에서의 신뢰성을 뒷 채널 표면 전위와 드바이 길이를 고려하여 연구 하였다. 먼저, 용액 공정 인듐갈륨징크 산화물 박막트랜지스터의 결함구조밀도를 추출하는 방법에 대해 연구하였다. 기존에 발표된 결함구조밀도 추출 방법들은 뒷 채널 표면 전위를 0으로 가정하였다. 이는 인가되는 게이트 전압의 영향을 충분히 차폐할 수 있을 정도로 반도체 층이 두꺼울 때에는 적절한 가정이다. 하지만 반도체 층이 드바이 길이보다 얇은 경우에는 뒷 채널 표면 전위가 게이트 전압에 의해 영향을 받을 수 있다. 용액 공정 기반 인듐갈륨징크 산화물 박막 트랜지스터의 경우 약 10 nm 정도의 매우 얇은 반도체 층으로 인해 뒷 채널의 표면 전위가 게이트 전압에 의해 영향을 받을 수 있기 때문에 이러한 가정은 수정이 필요하다. 따라서 뒷 채널 표면 전위를 0으로 가정하고 있는 기존의 추출 방법들은 정확한 결함구조밀도 추출을 위해 뒷 채널의 표면 전위를 고려하여 수정될 필요가 있다. 게이트 전압에 따른 뒷 채널 표면 전위의 변화는 스캐닝 켈빈 프로브 마이크로스코피로 측정 하였으며 기존의 필드 이펙트 방법을 수정하는 데에 사용 될 수 있도록 모델링 하였다. 뒷 채널 표면 전위를 고려하여 새롭게 수정된 필드 이펙트 방법은 기존의 방법에 비해 측정된 활성화 에너지 데이터와 더 일치하는 결과를 보여주었다. 기존의 추출 방법에서는 결함구조밀도가 실제보다 작은 수준으로 추출되는 반면, 수정된 필드 이펙트 방법 통해 더욱 정확히 용액 공정 기반 인듐갈륨징크 산화물 박막 트랜지스터의 결함구조밀도를 얻을 수 있었다. 개발한 결함구조밀도 추출 모델을 이용하여, 어닐링 온도, 조성 비율, 그리고 인듐갈륨징크 산화물 반도체 층의 두께 등 공정 및 소자 파라미터가 결함구조밀도에 미치는 영향에 대해 연구하였다. 다양한 공정 파라미터에 의한 소자의 전기적 특성 변화에 대해 재료적인 관점에서의 분석은 이루어졌지만, 이를 결함구조밀도와 같은 전기적으로 모델링을 하고 분석하는 것에 대한 연구는 아직 이루어지지 않은 상황이다. 이러한 파라미터들의 변화에 의한 소자의 동작을 정확히 분석하고 예측하기 위해서는 결함구조밀도의 변화 등을 전기적으로 모델링 할 필요가 있다. 어닐링 온도와 조성 비율이 변화함에 따라 결함구조밀도의 상대적으로 딥 레벨에 위치하는 스테이트와 테일 스테이트가 변화하였으며, 엑스선 광전자 분광법 결과와 비교를 통해 상대적으로 딥 레벨에 위치하는 스테이트는 산소 공핍 결합과, 테일 스테이트는 잔여 수산화물 결합과 각각 관련이 있다는 것을 알 수 있었다. 또한 다양한 두께의 반도체 층을 갖는 용액 공정 기반 인듐갈륨징크 산화물 박막트랜지스터의 결함구조밀도를 분석, 비교함으로써 핀홀과 같은 물리적 결함과 불규칙성이 테일 스테이트에 영향을 준다는 것을 알 수 있었다. 이러한 분석을 바탕으로 용액 공정 기반 인듐갈륨징크 산화물 반도체 박막 트랜지스터의 반도체 층 결함의 원인을 나타내는 결함구조밀도 맵을 얻을 수 있었다. 마지막으로, 정전압 스트레스에서의 용액 공정 인듐갈륨징크 산화물 박막트랜지스터의 신뢰성에 대해 연구하였다. 양의 게이트 전압 스트레스에서 문턱 전압은 양의 방향으로 이동하였으며, 진공 증착 기반 인듐갈륨징크 산화물 박막트랜지스터와 비슷한 양상을 보였다. 그러나 음의 전압 스트레스에서는 진공 증착 기반 인듐갈륨징크 산화물 박막트랜지스터와 달리 문턱 전압은 스트레스 시간에 따라 선형적으로 변화하였다. 이러한 열화 현상을 분석하기 위하여, 다른 반도체 층 두께와 드바이 길이를 갖는 소자의 신뢰성 측정, 그리고 흡착된 양 전하 물질이 소자의 전기적 특성에 미치는 영향에 대한 2차원 컴퓨터 시뮬레이션을 수행하였다. 그 결과, 음의 게이트 전압 스트레스에서 문턱전압이 선형적으로 이동하는 열화 현상은 공기 중의 양의 전하를 띄는 물질이 뒷 채널 영역에 흡착하는 것에 의한 것이라는 것을 확인 할 수 있었다.Amorphous metal oxide-based thin film transistors (TFTs) have attracted much attention as a most promising candidate for next generation electronic applications. Especially, amorphous indium gallium zinc oxide (IGZO) TFTs are expected to replace conventional silicon-based TFTs which encounter the limitation of electrical properties such as field-effect mobility, uniformity, and process temperature. In addition, there have been many efforts to fabricate IGZO TFTs using solution process to reduce process cost. However, device physics of solution-processed IGZO TFTs still needs to be investigated for further application. Furthermore, the effect of back channel surface region has been neglected in the analysis of IGZO TFTs. However, the back channel surface effect cannot be ignored when IGZO active layer is very thin, so that channel properties are affected by back channel surface. Therefore, the back channel surface effect needs to be considered in the analysis of solution-processed IGZO TFTs because solution-processed IGZO TFTs generally have very thin active layer, approximately 10~20 nm. In this thesis, device physical properties such as density-of-states (DOS) and reliability under bias stress of solution-processed IGZO TFTs are investigated with consideration of back channel surface potential and Debye length. First, the extraction model is developed to extract accurate DOS of solution-processed IGZO TFTs. In most previously reported DOS extraction methods, back channel surface potential (ΦB) was assumed to be zero. This assumption is appropriate when active layer is sufficiently thick to screen the effect of the applied gate voltage (VGS) on ΦB. On the contrary, ΦB is affected by VGS when active layer is thinner than Debye length. The assumption needs to be modified in the case of solution-processed IGZO TFTs, whose active layer is approximately 10 nm. Therefore, previously reported extraction method, which assumed zero potential at back channel surface, needs to be modified with consideration of ΦB for accurate DOS extraction. The variation of ΦB with VGS was measured by scanning Kelvin probe microscopy (SKPM) and modeled to be used for modification of conventional field-effect method. The modified field-effect method considering ΦB exhibited more consistent activation energy (Ea) extraction result with the measured data than conventional one. Accurate DOS of solution-processed IGZO TFTs was extracted with considering ΦB while conventional one underestimated the defect DOS. Second, the effect of process and device parameters on DOS was investigated with varying annealing temperature (Ta), metallic composition ratio or IGZO active layer thickness (tactive). The DOS of each device was extracted by the developed model. The electrical characteristics variation along with various process parameters has been analyzed in the aspect of material chemistry. However, the effect of those parameters on the electrical model such as DOS has not been studied yet. The electrical modeling such as DOS variation is required to simulate device operation accurately as process parameters change. As Ta and metallic composition ratio changed, the relatively deep and tail states of DOS were changed. By comparing the extracted DOS with x-ray photoelectron spectroscopy (XPS) results, it is found that relatively deep and tail states are related to oxygen vacancy and residual hydroxide in solution-processed IGZO film, respectively. It was also found that physical defects, such as pin-holes, and disorder affected tail states from the extracted DOS analysis of solution-processed IGZO TFTs with various tactive. From the DOS analysis, DOS map of solution-processed IGZO TFTs, which shows origins of relatively deep and tail states, is developed. Finally, the stability of solution-processed IGZO TFTs under constant gate bias stress is investigated. Under positive gate bias stress, the transfer characteristics of solution-processed IGZO TFTs were positively shifted and showed similar behavior compared to vacuum-processed IGZO TFTs. However, different behavior of threshold voltage shift (ΔVth) was observed under negative gate bias stress. The time evolution of ΔVth followed linear function. In order to analyze the reliability under negative gate bias stress, the stability of devices with different tactive and Debye length of IGZO layer was measured and the effect of adsorbed charged species on the electrical characteristics was simulated by 2-dimensional technology computer-aided design simulation. As a result, it is found that linear shift of Vth under negative gate bias stress is attributed to the adsorption of positively charged species on back channel surface region.Chapter 1 Introduction 1 1.1 Recent Flat Panel Display 1 1.2 Dissertation Organization 7 Chapter 2 Review of IGZO TFTs 9 2.1 Oxide Semiconductor for TFT Application 10 2.2 Various Extraction Methods of Density-of-States of TFTs 15 2.3 Process Parameter Variation of IGZO TFTs 24 2.4 Reliability of IGZO TFTs 28 Chapter 3 Development of Modified Field-Effect Method with Consideration of Back ChannelSurface Potential 32 3.1 Introduction 32 3.2 Experiment 35 3.2.1 Fabrication of Solution-Processed IGZO TFTs 35 3.2.2 Device and IGZO Film Characterization 40 3.2.3 Scanning Kelvin Probe Microscopy Measurement 40 3.3 Extraction of Density-of-States (DOS) of Solution-Processed IGZO TFTs with Consideration of Back Channel Surface Potential 43 3.3.1 Temperature-Dependent Electrical Characteristics 43 3.3.2 Back Channel Surface Potential of Solution-Processed IGZO TFTs 48 3.3.3 Modified Field-Effect Method Considering Back Channel Surface Potential 52 3.3.4 DOS Extraction of Solution-Processed IGZO TFTs by Modified Field-Effect Method Considering Back Channel Surface Potential 55 3.3.5 Verification of Assumption of Back Channel Surface Potential 59 3.4 Conclusion 63 Chapter 4 Effect of Process Parameters on DOS of Solution-Processed IGZO TFTs 64 4.1 Introduction 64 4.2 Experiment 66 4.3 Effect of Annealing Temperature on DOS of Solution-Processed IGZO TFTs 68 4.3.1 Device Characteristics 68 4.3.2 DOS Extraction Considering Back Channel Surface Potential and Analysis 77 4.4 Effect of Metallic Composition Ratio on DOS of Solution-Processed IGZO TFTs 84 4.4.1 Device Characteristics 84 4.4.2 DOS Extraction Considering Back Channel Surface Potential and Analysis 91 4.5 Effect of Active Layer Thickness on DOS of Solution-Processed IGZO TFTs 98 4.5.1 Device Characteristics 98 4.5.2 DOS Extraction Considering Back Channel Surface Potential and Analysis 104 4.6 DOS Mapping 110 4.7 Conclusion 112 Chapter 5 Analysis of Stability of Solution-Processed IGZO TFTs under Constant Gate Bias Stress 113 5.1 Introduction 113 5.2 Experiment 115 5.3 Stability under Negative Gate Bias Stress 116 5.4 Stability under Positive Gate Bias Stress 125 5.5 Conclusion 129 Chapter 6 Summary 130 Appendix A Circuit Application of Solution-Processed IGZO TFTs 134 Bibliography 149 초록 158Docto

Advanced Electrical Characterization of Oxide TFTs Design of a Temperature Compensated Voltage Reference

Any electronic device, regardless of its function, needs a reference voltage source that feeds reliably, i.e., which generates a constant voltage, upstream and regardless of external environmental conditions, such as temperature. Since such a characteristic negatively influences the behavior of the devices, whose base elements are transistors, it is essential to design a circuit that provides a voltage which is invariant over a temperature range. In this work is designed a circuit that is responsible for generating a reference voltage using only thin film transistors or TFTs, on glass substrate. However, in order to validate the concept used in the mentioned transistors, it is also dimensioned and simulated the proposed circuit in 130 nm CMOS technology, where the respective results are expected to be comparative between the two technologies. For CMOS technology, for a nominal reference voltage of 124,0 mV, Cadence simulation reveals ±2,2 ppm/ºC temperature coefficient, between -20 °C and 100 °C. The power consumptions are and 1,434 mW and 4,566 mW for both CMOS and IGZO-TFT technologies, respectively