Intelligent shop scheduling for semiconductor manufacturing

Semiconductor market sales have expanded massively to more than 200 billion dollars annually accompanied by increased pressure on the manufacturers to provide higher quality products at lower cost to remain competitive. Scheduling of semiconductor manufacturing is one of the keys to increasing productivity, however the complexity of manufacturing high capacity semiconductor devices and the cost considerations mean that it is impossible to experiment within the facility. There is an immense need for effective decision support models, characterizing and analyzing the manufacturing process, allowing the effect of changes in the production environment to be predicted in order to increase utilization and enhance system performance. Although many simulation models have been developed within semiconductor manufacturing very little research on the simulation of the photolithography process has been reported even though semiconductor manufacturers have recognized that the scheduling of photolithography is one of the most important and challenging tasks due to complex nature of the process. Traditional scheduling techniques and existing approaches show some benefits for solving small and medium sized, straightforward scheduling problems. However, they have had limited success in solving complex scheduling problems with stochastic elements in an economic timeframe. This thesis presents a new methodology combining advanced solution approaches such as simulation, artificial intelligence, system modeling and Taguchi methods, to schedule a photolithography toolset. A new structured approach was developed to effectively support building the simulation models. A single tool and complete toolset model were developed using this approach and shown to have less than 4% deviation from actual production values. The use of an intelligent scheduling agent for the toolset model shows an average of 15% improvement in simulated throughput time and is currently in use for scheduling the photolithography toolset in a manufacturing plant

IMPROVED PHOTOLITHOGRAPHY SCHEDULING IN SEMICONDUCTOR MANUFACTURING

Photolithography is typically the bottleneck process in semiconductor manufacturing. In this thesis, we present a model for optimizing photolithography job scheduling in the presence of both individual and cluster tools. The combination of individual and cluster tools that process various layers or stages of the semiconductor manufacturing process flow is a special type of flexible flowshop. We seek separately to minimize total weighted completion time and maximize on-time delivery performance. Experimental results suggest that our mathematical- and heuristic-based solution approaches show promise for real world implementation as they can help to improve resource utilization, reduce job completion times, and decrease unnecessary delays in a wafer fab

Cycle time prediction in the Wafer Test Fab of a semiconductor manufacturing plant using an artificial neural network model

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A review of data mining applications in semiconductor manufacturing

The authors acknowledge Fundacao para a Ciencia e a Tecnologia (FCT-MCTES) for its financial support via the project UIDB/00667/2020 (UNIDEMI).For decades, industrial companies have been collecting and storing high amounts of data with the aim of better controlling and managing their processes. However, this vast amount of information and hidden knowledge implicit in all of this data could be utilized more efficiently. With the help of data mining techniques unknown relationships can be systematically discovered. The production of semiconductors is a highly complex process, which entails several subprocesses that employ a diverse array of equipment. The size of the semiconductors signifies a high number of units can be produced, which require huge amounts of data in order to be able to control and improve the semiconductor manufacturing process. Therefore, in this paper a structured review is made through a sample of 137 papers of the published articles in the scientific community regarding data mining applications in semiconductor manufacturing. A detailed bibliometric analysis is also made. All data mining applications are classified in function of the application area. The results are then analyzed and conclusions are drawn.publishersversionpublishe

Traceable Standard for Sub - 100nm Metrology

As we approach the 65nm technological node, transistor gates with dimensions of the order of 40nm are being manufactured. As the device performance is directly related to the dimensions of the gate, critical dimension (CD) control becomes an important part of the fabrication process. Characterization of these small feature size, generally referred to as Metrology, is an indispensable ingredient of the semiconductor manufacturing processes. Metrology relies not only on the precision, but also the accuracy of commercially used metrology tools like the CD-SEM. To facilitate the magnification calibration of the CD-SEM, an easy access to standard reference artifact traceable to international specifications is an added advantage. Considerable literature is available for CD-SEM, which relies on in-house artifacts or general test objects. The absence of commercially available artifacts hinders evaluation of different CD-SEM. The objective of this abstract is to introduce the fabrication and characterization of artifacts for the sub-100nm metrology, which can be made available in wafer form at low cost. In this work, artifacts have been designed and fabricated for precise magnification calibration of the CD-SEM. The designing of the artifacts takes into account the proximity effect, a problem associated with the e-beam exposure, to produce dense grid type structure in the sub-100nm region. The structures are fabricated using the e-beam lithography tool, operated at 50KeV. The artifacts have been fabricated on a thin layer of negative resist HSQ spun on silicon substrate. Subsequent development in 0.26N TMAH gives a structure on silicon wafer, thereby eliminating contamination issues. Furthermore, characterization of the artifacts for line pitch determination is carried out using “Measure” (Spectel Corp.), which provides an absolute calibration of the image pixel size that can then be used to measure other features. The low values for the line edge roughness (LER) further facilitate precise linewidth metrology.\u3e/p\u3