III-V족 화합물 반도체 터널 전계 효과 트랜지스터 개발

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 최우영.리소그래피 기술의 놀라운 발전은 10 nm 이하의 논리 트랜지스터를 상용화했다. 게이트 길이 스케일링은 모스펫 (MOSFET)의 전력 소비를 줄이기 위한 노력의 큰 부분을 차지한다. 그러나 이러한 접근 방식은 리소그래피의 물리적 한계와 누설 전류 제어와 같은 몇 가지 문제에 직면했다. 모스펫의 근본적인 문제는 현재 전송 메커니즘의 한계로 인해 60 mV/dec 미만의 임계값 기울기 (SS)에 도달할 수 없다는 것이다. Si 터널링 전계효과 트랜지스터 (TFET)의 여러 연구자들이 60 mV/dec 미만의 결과를 보고했지만, Si 동종 접합 터널링 전계효과 트랜지스터는 간접 대역 갭 물질의 터널링 확률이 낮아 전류상으로 불충분하다. P-I 접합부에서의 터널링 확률은 터널링 전계효과 트랜지스터의 동작전류에 영향을 미치기 때문에 작은 직접 밴드갭을 가지고 유효질량이 낮은 III-V 화합물 반도체는 임계값 기울기가 60 mV/dec 미만인 높은 터널링 전류를 달성할 수 있는 가장 유망한 재료이다. 또한 밴드 오프셋이 다른 재료를 선택함으로써, 스태거드 또는 브로큰 갭을 형성함으로써 터널링 전류를 현저하게 증가시킬 수 있다. P-I 접합부의 터널링이 터널 전계효과 트랜지스터 소자의 전류 공급원이기 때문에 많은 연구자들이 분자빔 에피택시 (MBE) 방식으로 성장한 p형 도핑 농도가 높은 III-V 웨이퍼로 제조된 터널 전계효과 트랜지스터의 성능을 보고해왔다. 그러나 높은 도핑 농도와 가파른 도펀트 프로파일을 갖는 p형 InGaAs를 성장하기가 까다롭기 때문에 금속-유기 화학 기상 증착 (MOCVD) 성장 에피택셜 층에서 제조된 InGaAs TFET 소자는 거의 보고되지 않았다. 이에 따라 본 연구는 TFET 소자 제작을 위한 고품질 에피택셜 층을 성장시키기 위한 MOCVD 성장 기술을 선보인다. 종래의 TFET 소자에 대해서는 동종 접합 p-i-n InGaAs 에피택셜층을 성장시키고, p++-Ge/i-InGaAs/n+-InAs 나노선을 성장시켜 TFET 소자 성능 향상 가능성을 확인하였다. MOCVD에 의해 성장한 에피택시 층에서 제조된 TFET 소자의 잠재성을 확인하기 위해 평판과 나노선 에피택셜 층에서 제작된 TFET 소자의 성능이 확인되었다. MOCVD 방법을 이용하여 고품질의 에피택셜 층이 성장되었다. MBE에 비해 가성비, 높은 처리량, 우수한 결정 품질이 MOCVD의 가장 큰 장점이다. 이에 여러 성장 조건을 변화시키면서 InP (001) 기판 위로 InGaAs 필름층의 성장이 연구되었다. 소스 유량, 온도 및 V/III 비율이 성장된 InGaAs 필름층의 품질에 끼치는 영향이 연구되었다. 또한 MOCVD InGaAs 성장 기술에서 n형 및 p형 도펀트의 농도를 높이는 것과 도펀트 프로파일을 가파르게 하는 것이 도전적이므로 탄소 및 텔루륨 도핑을 통해 가파른 도펀트 프로파일을 보이는 고농도의 p형 및 n형 InGaAs층을 성장하였다. 성장된 에피택셜 필름층은 TFET 소자를 제작하여 평가하였다. TFET 소자 제작 전에 우선 TFET 소자의 채널 길이가 전기적 시뮬레이션 결과에 의해 선택되었다. MOCVD를 이용하여 도핑 프로파일이 가파른 고품질의 수직 p-i-n 에피텍셜 구조가 한번에 성장되었다. 에피택셜 성장 후에 TFET 소자는 수직 방향의 습식 식각을 통해 제작되었다. 옴 (Ohmic) 공정과 에어브릿지 공정도 소자 제작을 위해 최적화되었다. P형 도핑 농도에 대한 영향과 MOCVD 성장 중에 생긴 전위에 대한 영향이 TFET 성능을 통하여 확인되었다. 제조된 TFET 소자는 60 mV/dec에 가까운 SS와 괜찮은 온/오프 전류 비율을 보여주었는데, 이는 최초로 보고되는 MBE에서 성장된 웨이퍼에서 만들어진 TFET 소자와 비교할 수 있는 소자이다. 이 결과는 고품질의 MOCVD로 성장한 III-V TFET 소자의 양산 가능성을 보여준다. 이 연구의 다음 부분은 나노선 TFET 제작이다. 전자소자 제작을 위한 III-V 나노선 성장에는 몇 가지 장점이 있다. 다양한 종류의 웨이퍼에 다양한 특성을 가지는 헤테로 구조를 형성할 수 있다는 것이 큰 장점이다. 충분히 작은 직경으로 성장된 나노선은 웨이퍼와 다른 격자 상수를 가지더라도 전위 없는 계면을 가진다. 다양한 유형의 밴드 정렬이 만들어질 수 있으며, 이는 TFET의 터널링 정류를 증가시키는 데에 있어 중요한 요소이다. 또한 직경이 작은 나노선은 칩으로 제작되었을 때 더 나은 소자 밀도, 향상된 게이트 제어성, 성장 시간 단축을 통한 처리량 향상이 가능하다. InGaAs 나노선은 선택적 영역 성장법 (SAG) 성장되었다. 하드마스크 층으로서 InP (111)B 및 Ge (111) 웨이퍼에 SiO2 층이 증착 되었다. 성장 모드가 다르기 때문에 InGaAs 평판 필름층 성장과는 크게 다른 성장 조건을 테스트하였다. 나노선의 선택적 성장은 온도, V/III 비율 및 소스 유량을 최적화하여 확인하였다. 그 결과 InP (111)B와 Ge (111) 웨이퍼에서 InAs와 InGaAs 나노선을 성공적으로 성장시켰다. P형 물질로는 p++도핑된 Ge (111) 웨이퍼를 사용하였다. 인트린식 InGaAs와 InAs 나노선이 그 위에 선택적으로 성장되었다. 마지막으로 실리콘 도펀트를 가진 n형 InAs 나노선이 후속적으로 성장되었다. 성장된 나노선은 수직 나노선 TFET을 제작하여 평가되었다. 높은 단계 커버리지와 양호한 인터페이스 상태 밀도를 위하여 ALD HfO2 및 ALD TiN 공정과정이 최적화되었다. 개발된 ALD 공정을 적용함으로써 수직형 나노선 Ge/InGaAs 헤테로 접합 TFET의 동작이 성공적으로 확인되었다.The remarkable development of lithography technology commercialized the sub-10 nm logic transistors. Gate length scaling is a large portion of the effort to reduce the power consumption of metal-oxide-semiconductor field-effect transistors (MOSFETs). However, this approach faces several problems, such as the physical limitation of lithography and leakage current control. The fundamental problem of MOSFETs is that they cannot reach subthreshold-slope (SS) below 60 mV/dec due to their current transport mechanism. Several researchers of Si tunneling field-effect transistors (TFETs) reported sub-60 mV/dec, but Si homo-junction TFETs show insufficient on-current due to the poor tunneling probability of indirect-band gap materials. As tunneling probability at the p-i junction influences the on-current of TFETs, III-V compound semiconductors, which have a direct small band gap and low effective masses, are the most promising materials to achieve high tunneling current with SS below 60 mV/dec. Also, the tunneling current can be remarkably increased by forming a staggered or broken gap by choosing materials with different band offsets. Since the tunneling at a p-i junction is the current source of TFET devices, many researchers have reported the performance of TFETs fabricated from III-V wafers with high p-type doping concentration grown by the molecular beam epitaxy (MBE) method. However, very few InGaAs TFET devices fabricated on MOCVD-grown epitaxial layers have been reported due to the challenging techniques for achieving p-type InGaAs with high doping concentration and steep dopant profile. Accordingly, this work demonstrates the metal-organic chemical vapor deposition (MOCVD) growth techniques to grow a high-quality epitaxial layer for TFET device fabrication. Homo-junction p-i-n InGaAs epitaxial layers were grown for conventional TFET devices, and hetero-junction p++-Ge/i-InGaAs/n+-InAs nanowires were grown to confirm the possibility of boosting the TFET device performance. The TFET device performance at both epitaxial layers was characterized to confirm the potential of TFET devices fabricated on the epitaxy layers grown by the MOCVD method. The high-quality epitaxial layers were grown using the MOCVD method. Compared to the MBE method, cost-effectiveness, high throughput, and excellent crystal quality are the significant advantages of the MOCVD method. The growth of InGaAs film layers on InP (001) substrate with several growth conditions was studied. The effects of source flow rate, temperature, and V/III ratio on the quality of grown InGaAs film layers were studied. As the high-concentration and steep dopant profile of n-type and p-type dopants are challenging in MOCVD InGaAs growth technique, carbon and tellurium doping techniques were introduced to achieve highly-doped p-type and n-type InGaAs layer with steep dopant profile. The grown epitaxial film layers were evaluated by fabricating the TFET device. Before the TFET device fabrication, the dimensions of the TFET device were selected by electrical simulation results of TFET devices with different structures. For TFET device fabrication, a high-quality vertical p-i-n epitaxial structure with a steep doping profile was successively formed by MOCVD. After epitaxial growth, the TFET devices were fabricated by the vertical top-down wet etching method. The ohmic process and air-bridge process were also optimized for device fabrication. The effect of p-type doping concentration and the dislocations formed during MOCVD growth was confirmed by TFET performance. The fabricated TFET devices showed SS of near-60 mV/dec and sound on/off current ratio, which was by far the first reported device comparable to TFET devices fabricated on the MBE-grown wafers. This result represents the possible mass-production of high-quality MOCVD-grown III-V TFET devices. The next part of this study is nanowire TFET fabrication. The growth of III-V nanowires for electronic device fabrication has several advantages. The significant advantage is that hetero-structures with various characteristics can be formed on various wafers. The nanowires grown by a sufficiently small diameter show a dislocation-free interface even if nanowires have a different lattice constant compared to the wafer. Various types of band-alignment can be formed, and this is a crucial factor in boosting the tunneling current of TFETs. Also, nanowires with a small diameter show better device density in a chip, improved gate controllability, and enhanced throughput by reducing growth time. The InGaAs nanowires were grown by the selective area growth (SAG) method. As a hard-mask layer, a SiO2 layer was deposited on InP (111)B and Ge (111) wafers. Growth conditions far different from InGaAs film layer growth were tested due to the different growth modes. Selective growth of nanowires was identified by optimizing temperature, V/III ratio, and source flow rate. As a result, InAs and InGaAs nanowires were successfully grown on InP (111)B and Ge (111) wafers. For p-type material, the p++-doped Ge (111) wafer was used. The intrinsic InGaAs and InAs nanowires were selectively grown on the patterned substrate. Finally, n-type InAs nanowires with silicon dopant were grown subsequently. The grown nanowires were evaluated by fabricating the vertical nanowire TFETs. ALD HfO2 and ALD TiN processes were optimized for high step coverage and good interface state density. By applying the developed ALD processes, a successful demonstration of vertical nanowire Ge/InGaAs hetero-junction TFET was observed.Contents List of Tables List of Figures Chapter 1. Introduction 1 1.1. Backgrounds 1 1.2. III-V TFETs for Low Power Device 5 1.3. Epitaxy of III-V Materials 12 1.4. Research Aims 17 1.5. References 20 Chapter 2. Epitaxial Growth of InGaAs on InP (001) Substrate 24 2.1. Introduction 24 2.2. Temperature Dependent Properties of Intrinsic-InGaAs on InP (001) Substrate 33 2.3. In-situ Doping Properties of InGaAs on InP (001) Substrate 37 2.4. Conclusion 51 2.5. References 52 Chapter 3. Demonstration of TFET Device Fabricated on InGaAs-on-InP (001) Substrate 56 3.1. Introduction 56 3.2. Simulation of Basic Operations of TFET Device 60 3.3. Process Optimization of TFET Fabrication 68 3.4. Process Flow 74 3.5. Characterization of TFETs Fabricated on MBE-grown and MOCVD-grown Wafers 78 3.6. Conclusion 96 3.7. References 97 Chapter 4. Selective Area Growth of In(Ga)As Nanowires 101 4.1. Introduction 101 4.2. Process Flow of Nanowire Growth 108 4.3. Impact of Different Growth Variables on the Growth of InAs Nanowires 113 4.4. Impact of Different Growth Variables on the Growth of InGaAs Nanowires 127 4.5. Conclusion 144 4.6. References 146 Chapter 5. Demonstration of Vertical Nanowire TFET 149 5.1. Introduction 149 5.2. Optimization of ALD HfO2 High-k Stack 152 5.3. Optimization of ALD TiN Gate Metal 169 5.4. Detailed Demonstration of Vertical Nanowire TFET Fabrication Processes 182 5.5. Characterization of Fabricated Vertical Nanowire TFETs 196 5.6. Conclusion 203 5.7. References 205 Chapter 6. Conclusions and Outlook 209 6.1. Conclusions 209 6.2. Outlook 211 Appendix. 213 A. n+-InAs Nanowire Doping Concentration Evaluation by TLM Method 213 B. n+-InAs Nanowire Doping Concentration Evaluation by C-V Method 219 C. References 205 Abstract in Korean 226 Research Achievements 230박

Investigation of Gate Dielectric Materials and Dielectric/Silicon Interfaces for Metal Oxide Semiconductor Devices

The progress of the silicon-based complementary-metal-oxide-semiconductor (CMOS) technology is mainly contributed to the scaling of the individual component. After decades of development, the scaling trend is approaching to its limitation, and there is urgent needs for the innovations of the materials and structures of the MOS devices, in order to postpone the end of the scaling. Atomic layer deposition (ALD) provides precise control of the deposited thin film at the atomic scale, and has wide application not only in the MOS technology, but also in other nanostructures. In this dissertation, I study rapid thermal processing (RTP) treatment of thermally grown SiO2, ALD growth of SiO2, and ALD growth of high-k HfO2 dielectric materials for gate oxides of MOS devices. Using a lateral heating treatment of SiO2, the gate leakage current of SiO2 based MOS capacitors was reduced by 4 order of magnitude, and the underlying mechanism was studied. Ultrathin SiO2 films were grown by ALD, and the electrical properties of the films and the SiO2/Si interface were extensively studied. High quality HfO2 films were grown using ALD on a chemical oxide. The dependence of interfacial quality on the thickness of the chemical oxide was studied. Finally I studied growth of HfO2 on two innovative interfacial layers, an interfacial layer grown by in-situ ALD ozone/water cycle exposure and an interfacial layer of etched thermal and RTP SiO2. The effectiveness of growth of high-quality HfO2 using the two interfacial layers are comparable to that of the chemical oxide. The interfacial properties are studied in details using XPS and ellipsometry

Ferroelectric-Semiconductor Systems for New Generation of Solar Cells

This dissertation includes two parts. In the first part the study is focused on the fabrication of multifunctional thin films for photovoltaic applications. There is no doubt about the importance of transforming world reliance from traditional energy resources, mainly fossil fuel, into renewable energies. Photovoltaic section still owns very small portion of the production, despite its fast growth and vast research investments. New methods and concepts are proposed in order to improve the efficiency of traditional solar cells or introduce new platforms. Recently, ferroelectric photovoltaics have gained interest among researchers. First objective in application of ferroelectric material is to utilize its large electric field as a replacement for or improvement of built-in electric field in semiconductor p-n junctions which is responsible for the separation of generated electron-hole pairs. Increase in built in electric field will increase open-circuit voltage of the solar cell. In this regard, thin films of ferroelectric hafnium dioxide doped with silicon have been fabricated using physical vapor deposition techniques. Scanning probe microscopy techniques (PFM and KPFM) have been employed to analyze ferroelectric response and surface potential of the sample. The effects of poling direction of the ferroelectric film on the surface potential and current-voltage characteristics of the cell have been investigated. The results showed that the direction of poling affects photoresponse of the cell and based on the direction it can either improved or diminished. In the second part of this work, epitaxial thin films have been synthesized with physical vapor deposition techniques such as sputtering and electron beam evaporation for the ultimate goal of producing multifunctional three-dimensional structures. Three-dimensional structures have been used for applications such as magnetic sensors, filters, micro-robots and can be used for modification of the surface of solar cells in order to improve light absorption and efficiency. One of the important techniques for producing 3-D structures is using origami techniques. The effectiveness of this technique depends on the control of parameters which define direction of bending and rolling of the film or curvature of the structure based on the residual stress in the structure after film’s release and on the quality and uniformity of the film. In epitaxially grown films, the magnitude and direction of the stress are optimized, so the control over direction of rolling or bending of the film can be controlled more accurately. For this purpose, deposition conditions for epitaxy of Zn, Fe, Ru, Ti, NaCl and Cr on Si, Al2O3 or MgO substrates have been investigated and optimized. Crystallinity, composition and morphology of the films were characterized using reflective high energy diffraction (RHEED), Auger electron spectroscopy (AES), energy dispersive X-ray (EDX), and scanning electron microscopy (SEM)

LARGE-AREA, WAFER-SCALE EPITAXIAL GROWTH OF GERMANIUM ON SILICON AND INTEGRATION OF HIGH-PERFORMANCE TRANSISTORS

Building on a unique two-step, simple MBE growth technique, we have investigated possible dislocation locking mechanisms by dopant impurities, coupled with artificially introduced oxygen. In the case of n-type Ge grown on Si, our materials characterization indicates that the dislocation density (DD) can reach the \uf07e105 cm-2 level, compared to p-type and undoped Ge on Si (GoS). We note that our Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. In this presentation, we will focus on the use of n-type impurity (phosphorus) diffusing from the Si substrate and the introduction of O at the Ge-Si interface. The O is introduced by growing a thin chemical SiO2 layer on top of the Si substrate before Ge epitaxy begins. Z-contrast cross-sectional TEM images suggest the presence of oxygen precipitates in n-type Ge, whereas these precipitates appear absent in p-type Ge. These oxygen precipitates are known to lock the dislocations. Supporting the argument of precipitate formation, the TEM shows fringes due to various phase boundaries that exist at the precipitate/Ge-crystal interface. We speculate that the formation of phosphorus (P) segregation resulting from slow diffusion of P through precipitates at the precipitate/Ge-crystal interface facilitates dislocation locking. Impurity segregations in turn suppress O concentration in n-type Ge indicating reduced magnitude of DD that appears on the top surface of n-Ge compared to p-Ge film. The O concentrations (1017 to 1018 cm-3) in the n- and p-type GoS films are measured using secondary ionization mass spectroscopy. We also demonstrate the technique to improve the Ge epitaxial quality by inserting air-gapped, SiO2-based nanoscale templates within epitaxially grown Ge on Si. We have shown that the template simultaneously filters threading dislocations propagating from Ge-Si interface and relieves the film stress caused by the TEC mismatch. The finite element modeling stress simulation shows that the oval air gaps around the SiO2 template can reduce the thermal stress by 50% and help reduce the DD. We have then compared the structural and electrical characteristics of n-type Ge films with its p-type counter parts. In n-type Ge, the DD decreases from \uf07e109cm-2 near the Ge-Si interface to \uf07e105 cm-2 at the film surface. In contrast, we observe 5\uf0b4107 cm-2 TDD at the film surface in p-type Ge. The full width at half-maximum for our n-type Ge(004) XRD peak is ~70% narrower than that of p-type Ge. As a stringent test of the dislocation reduction, we have also fabricated and characterized high-carrier-mobility MOSFETs on GoS substrates. We also report p- and n-MOSFETs with μeff of 401 and 940 cm2/V-s and a subthreshold slope of 100 and 200 mV/decade, respectively. These effective mobilities show an exceptional 82 and 30% improvement over that of conventional Si channel MOSFETs. We also investigate the optical quality of ultra-low DD GoS film by measuring photoluminescence (PL). The n-type Ge PL main peak shows pronounced tensile-strain (x0.8%) than that of p-type which is an indicator of direct BG shrinking at the \u0413 band-edge. Going beyond epitaxial engineering and device fabrication, we have also recently demonstrated a scalable path to create a 2D array of Ge quantum dots (QDs) on responsive SiGe substrates based on elastic mechanical deformation and subsequent SiGe compositional redistribution, coupled with MBE growth. For large-scale manufacturing of single-electron transistors, we have also demonstrated that a spatially structured elastic compressive stress to the SiGe substrate with thermally annealing leads to a compositional redistribution of Si and Ge in the near-surface region of SiGe substrates, forming a 2D array of Ge-depleted nanoscale regions. Based on these latest findings, we have also begun to chart a future direction for my research group, where one can explore new advanced device architectures, such as Si-compatible, optically actuated, Ge-quantum dot-based field effect transistors

Atomic layer deposition of metal oxide thin films and nanostructures

Ankara : Materials Science and Nanotechnology Program of Graduate School of Engineering and Science of Bilkent University, 2013.Thesis (Master's) -- Bilkent University, 2013.Includes bibliographical references leaves 82-89.With the continuing scaling down of microelectronic integrated circuits and increasing need for three-dimensional stacking of functional layers, novel or improved growth techniques are required to deposit thin films with high conformality and atomic level thickness control. As being different from other thin film deposition techniques, atomic layer deposition (ALD) is based on selflimiting surface reactions. The self-limiting film growth mechanism of ALD ensures excellent conformality and large area uniformity of deposited films. Additionally, film thickness can be accurately controlled by the number of sequential surface reactions. Gallium oxide (Ga2O3) thin films were deposited by plasma-enhanced ALD (PEALD) using trimethylgallium as the gallium precursor and oxygen plasma as the oxidant. A wide ALD temperature window was observed from 100 to 400 °C, where the deposition rate was constant at ~0.53 Å/cycle. The deposition parameters, composition, crystallinity, surface morphology, optical and electrical properties were studied for as-deposited and annealed Ga2O3 films. In order to investigate the electrical properties of the deposited films, metal-oxide-semiconductor capacitor structures were fabricated for a variety of film thicknesses and annealing temperatures. Ga2O3 films exhibited decent dielectric properties after crystallization upon annealing. Dielectric constant was increased with film thickness and decreased slightly with increasing annealing temperature. As an additional PEALD experiment, deposition parameters of In2O3 thin films were studied as well, using the precursors of cyclopentadienyl indium and O2 plasma. Initial results of this experiment effort are also presented. Accurate thickness control, along with high uniformity and conformality offered by ALD makes this technique quite promising for the deposition of conformal coatings on nanostructures. This thesis also deals with the synthesis of metal oxide nanotubes using organic nanofiber templates. Combination of electrospinning and ALD processes provided an opportunity to precisely control both diameter and wall thickness of the synthesized nanotubes. As a proof-ofconcept, hafnia (HfO2) nanotubes were synthesized using three-step approach: (i) preparation of the nylon 6,6 nanofiber template by electrospinning, (ii) conformal deposition of HfO2 on the electrospun polymer template via ALD using the precursors of tetrakis(dimethylamido)hafnium and water at 200 °C, and (iii) removal of the organic template by calculation to obtain freestanding HfO2 nanotubes (hollow nanofibers). When the same deposition procedure was applied on nanofibers with different average fiber diameters, thinner HfO2 wall thicknesses were obtained for the templates having smaller diameters due to insufficient exposure of precursor molecules to saturate their extremely large surface area. Thus, “exposure mode” was applied to obtain the desired wall thickness while coating high-surface area nanofibers. We present the experimental efforts including film deposition parameters, structural, elemental, and morphological properties of HfO2 nanotubes.Dönmez, İnciM.S

Novel Materials for Post-Silicon Electronics: 2D Semiconductors, Perovskite Dielectrics, and Metal-Organic Frameworks

Over the past five decades, the progress of scaling down metal-oxide-semiconductor field-effect transistors (MOSFETs) has been the main reason for boosting the performance of most electronic products we use. However, ultrascaled MOSFETs suffer from many issues related to fundamental quantum limitations imposed by extreme minification. Two main strategies are proposed to address these problems: (1) The first one is to pile electronic device layers that can compute data vertically, i.e., 3D integration; hence more operations can be implemented in the same area. 3D integration considerably relies on the back-end-of-line (BEOL) process, where dense metal interconnects result in the aggravated resistive-capacitive (RC) delay. To solve this problem, new low-κ gap-filling materials are required. Metal-organic frameworks (MOFs) are emerging coordination compounds consisting of metal ion nodes connected by organic linkers with repeating coordination. The rigid ionic bonds and orderly porous structures give MOFs particular mechanical strength and low permittivity to be a potential candidate. In addition, designable functionality enables MOF to serve as versatile active components. However, major preparations for MOF coatings are solution-based routes, making them incompatible with advanced semiconductor fabrications whose features are getting smaller and deeper. (2) Another strategy is implementing low-dimensional semiconductors to replace silicon as the transistor channel because of their talent for being atomically thin without degrading performance. Although 2D transition metal dichalcogenides (TMDCs) are recognized as the most promising among several candidates, there are still a number of challenges to be addressed before practically adopting them in the industry. In this thesis, a low-temperature chemical vapor deposition (CVD) synthetic method of MOFs is demonstrated, which can be implemented as low-κ gap-filling materials in increasingly important BEOL processes and active material in chemical sensors. Furthermore, this thesis exhibits the integration of single-crystal SrTiO3 gate dielectric in the monolayer CVD MoS2 FETs. The high-permittivity natural of SrTiO3 facilitates the gate controllability for ultrascaled transistors. The devices manifest good reliability and competitive performance characteristics, including a steep subthreshold swing (SS) of 70 mV/dec and a large ON/OFF current ratio of 1E7

Roadmap on ferroelectric hafnia- and zirconia-based materials and devices

Ferroelectric hafnium and zirconium oxides have undergone rapid scientific development over the last decade, pushing them to the forefront of ultralow-power electronic systems. Maximizing the potential application in memory devices or supercapacitors of these materials requires a combined effort by the scientific community to address technical limitations, which still hinder their application. Besides their favorable intrinsic material properties, HfO2–ZrO2 materials face challenges regarding their endurance, retention, wake-up effect, and high switching voltages. In this Roadmap, we intend to combine the expertise of chemistry, physics, material, and device engineers from leading experts in the ferroelectrics research community to set the direction of travel for these binary ferroelectric oxides. Here, we present a comprehensive overview of the current state of the art and offer readers an informed perspective of where this field is heading, what challenges need to be addressed, and possible applications and prospects for further development