Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed

Structured modeling for VHDL synthesis

This report will describe a proposed modeling style for the use of the VHSIC Hardware Description Language (VHDL) in design synthesis. We will describe the operations and underlying assumptions of four design models currently understood and used in practice by designers: combinational logic, functional descriptions (involving clocked components such as counters), register transfer (data path) descriptions, and behavioral (instruction set or processor) designs. We will illustrate the various uses of the VHDL description styles (structural, dataflow and behavioral) to represent characteristics of each of these design models. Emphasis is placed on how VHDL constructs should be used in order to synthesize optimal designs

High-Performance Passive Macromodeling Algorithms for Parallel Computing Platforms

This paper presents a comprehensive strategy for fast generation of passive macromodels of linear devices and interconnects on parallel computing hardware. Starting from a raw characterization of the structure in terms of frequency-domain tabulated scattering responses, we perform a rational curve fitting and a postprocessing passivity enforcement. Both algorithms are parallelized and cast in a form that is suitable for deployment on shared-memory multicore platforms. Particular emphasis is placed on the passivity characterization step, which is performed using two complementary strategies. The first uses an iterative restarted and deflated rational Arnoldi process to extract the imaginary Hamiltonian eigenvalues associated with the model. The second is based on an accuracy-controlled adaptive sampling. Various parallelization strategies are discussed for both schemes, with particular care on load balancing between different computing threads and memory occupation. The resulting parallel macromodeling flow is demonstrated on a number of medium- and large-scale structures, showing good scalability up to 16 computational core

Wavelet-Based High-Order Adaptive Modeling of Lossy Interconnects

Abstract—This paper presents a numerical-modeling strategy for simulation of fast transients in lossy electrical interconnects. The proposed algorithm makes use of wavelet representations of voltages and currents along the structure, with the aim of reducing the computational complexity of standard time-domain solvers. A special weak procedure for the implementation of possibly dynamic and nonlinear boundary conditions allows to preserve stability as well as a high approximation order, thus leading to very accurate schemes. On the other hand, the wavelet expansion allows the computation of the solution by using few significant coefficients which are automatically determined at each time step. A dynamically refinable mesh is then used to perform a sparse time-stepping. Several numerical results illustrate the high efficiency of the proposed algorithm, which has been tuned and optimized for best performance in fast digital applications typically found on modern PCB structures. Index Terms—Finite difference methods, time-domain analysis, transmission lines, wavelet transforms. I

On the Generation of Large Passive Macromodels for Complex Interconnect Structures

This paper addresses some issues related to the passivity of interconnect macromodels computed from measured or simulated port responses. The generation of such macromodels is usually performed via suitable least squares fitting algorithms. When the number of ports and the dynamic order of the macromodel is large, the inclusion of passivity constraints in the fitting process is cumbersome and results in excessive computational and storage requirements. Therefore, we consider in this work a post-processing approach for passivity enforcement, aimed at the detection and compensation of passivity violations without compromising the model accuracy. Two complementary issues are addressed. First, we consider the enforcement of asymptotic passivity at high frequencies based on the perturbation of the direct coupling term in the transfer matrix. We show how potential problems may arise when off-band poles are present in the model. Second, the enforcement of uniform passivity throughout the entire frequency axis is performed via an iterative perturbation scheme on the purely imaginary eigenvalues of associated Hamiltonian matrices. A special formulation of this spectral perturbation using possibly large but sparse matrices allows the passivity compensation to be performed at a cost which scales only linearly with the order of the system. This formulation involves a restarted Arnoldi iteration combined with a complex frequency hopping algorithm for the selective computation of the imaginary eigenvalues to be perturbed. Some examples of interconnect models are used to illustrate the performance of the proposed technique

Chip level simulation of fault tolerant computers

Chip level modeling techniques, functional fault simulation, simulation software development, a more efficient, high level version of GSP, and a parallel architecture for functional simulation are discussed