Comparative analysis of VDMOS/LDMOS power transistors for RF amplifiers

A comparison between the RF performance of vertical and lateral power MOSFETs is presented. The role of each parasitic parameter in the assessment of the power gain, 1-dB compression point, efficiency, stability, and output matching is evaluated quantitatively using new analytical expressions derived from a ten-element model. This study reveals that the contribution of the parasitic parameter on degradation of performance depends upon the specific technology and generic perceptions of source inductance and feedback capacitance in VDMOS degradation may not always hold. This conclusion is supported by a detailed analysis of three devices of the same power rating from three different commercial vendors. A methodology for optimizing a device technology, specifically for RF performance and power amplifier performance is demonstrated

Physics and technologies of silicon LDMOSFET for radio frequency applications

This thesis is devoted to the investigation of devices and technologies of Lateral Double-Diffused- Metal-Oxide-Semiconductor-Field-Effect-Transistor for Radio Frequency (RP) applications. Theoretical analysis and extensive 2-D process and device simulation results are presented. Theoretical analysis and simulations are carried out on RESURF LDMOS in both bulk and SOI substrate in terms of breakdown characteristics, transconductance, on resistance and CV characteristics. Quasi-saturation is a common phenomenon in DMOS devices. In this work, the dependence of quasi-saturation current on device physical and geometrical parameters is investigated in SOI RP LDMOS. Physical insight is gained into quasi-saturation on SOI RP LDMOS with different top silicon thickness and the same drift dose. It reveals that the difference in thick and thin film SOI lies in the different potential drop in the drift region. The influence of RESURF effect on quasi-saturation is also presented. It is shown that quasi-saturation current level can be affected by RESURF due to its influence on the drift dose. The mechanism of self-heating is presented and the influence of top silicon thickness, buried oxide thickness, voltage bias is studied through simulations. The change of peak temperature and its location with bias is due to the shift of electric field with voltage bias. A back-etch structure and fabrication process have been proposed to achieve a superior thermal performance. The negative differential conductance is not present in the non-isothermal IV curves. The temperature rise in the back-etch structure is less than 114 of that in the bulk structure. An RP LDMOS with a step drift doping profile on SIMOX substrate is evaluated. The fabrication process for the drift formation is proposed. The presented results demonstrate that step drift device has higher breakdown voltage than the conventional uniformly doped (UD) device, which provides the possibility to integrate LDMOS with low voltage CMOS for 28V base station application. This structure also has the advantage of suppressed kink effect due to the reduced electric field within the drift region. The step drift structure also features lower capacitance, improved drain current saturation behaviour and reduced self-heating at class AB bias point. For the first time, a novel sandwich structure for lateral RF MOSFET has been analysed based on silicon-on-nothing (SON) technology. The influence of device parameters on BV, CV and thermal performance has been investigated. Partial SON structure is found preferable in terms of heat conduct ability. Comparison on the electrical and thermal performance is made between SON LDMOSFET and conventional SOI alternative with BV of 40V. It is found that SON structure shows improvement in output capacitance and substrate loss. However, the temperature rise in SON device is higher compared to SOI alternative. The performance of the proposed sandwich SON structure has also been investigated in 28V base station applications, which requires breakdown voltage of 80V

On the design and linearization of transmitters for the LTE 450 base station

The paper presents the two transmitter analog paths of 10 W and 400 W peak output power developed for micro- and macro-cell LTE450 base stations, respectively. Each path contains a chain of amplifiers with a final stage designed in the Doherty architecture to improve total transmitter power efficiency. The paths were optimized for linearity and efficiency considering, i.e., an output power vs. input power course shape and tuning of the amplifier\u27s operating points while using low computational complexity MP algorithms

DESIGN OF LOW POWER MOBILE TRANSMITTER

The objective of this project is to design a power amplifier for a new two way mobile radio product being launched by Motorola. Two-way mobile radio consists of a transmitter, receiver and a voltage-controlled oscillator. Mobile radios usually have transmitter whose power output ranges from 1 W to 50 W. Design of transmitter lineup for mobile radio involves the design of appropriate matching network for driver and power amplifier. The power and voltage control of these devices are equally important. Designing a mobile radio transmitter is regarded tricky due to difficulty in getting a robust transmitter that is stable with minimum oscillation. In this work, the design is attempted usmg Advanced Design Simulator (ADS). The design simulation provides accurate simulation on harmonic filter and antenna switch. 50 ohm matching networks have also been designed and simulated using ADS and it gives close approximation to the specifications. The radio has since been prototyped and tested. The evaluation and testing of the radio has been carried out and it satisfies the specifications that are set by the Telecommunication Industry Association (TIA). Some minor optimization has also been performed to improve the radio performance. Eventual product is a transmitter line up that function well today. 11

Fast physical models for Si LDMOS power transistor characterization

A new nonlinear, process-oriented, quasi-two-dimensional (Q2D) model is described for microwave laterally diffused MOS (LDMOS) power transistors. A set of one-dimensional energy transport equations are solved across a two-dimensional cross-section in a “current-driven” form. The model accounts for avalanche breakdown and gate conduction, and accurately predicts DC and microwave characteristics at execution speeds sufficiently fast for circuit simulation applications

DESIGN OF LOW POWER MOBILE TRANSMITTER

The objective of this project is to design a power amplifier for a new two way mobile radio product being launched by Motorola. Two-way mobile radio consists of a transmitter, receiver and a voltage-controlled oscillator. Mobile radios usually have transmitter whose power output ranges from 1 W to 50 W. Design of transmitter lineup for mobile radio involves the design of appropriate matching network for driver and power amplifier. The power and voltage control of these devices are equally important. Designing a mobile radio transmitter is regarded tricky due to difficulty in getting a robust transmitter that is stable with minimum oscillation. In this work, the design is attempted usmg Advanced Design Simulator (ADS). The design simulation provides accurate simulation on harmonic filter and antenna switch. 50 ohm matching networks have also been designed and simulated using ADS and it gives close approximation to the specifications. The radio has since been prototyped and tested. The evaluation and testing of the radio has been carried out and it satisfies the specifications that are set by the Telecommunication Industry Association (TIA). Some minor optimization has also been performed to improve the radio performance. Eventual product is a transmitter line up that function well today. 11

A very low distortion high efficiency class-F power amplifier at 900 MHz.

This paper presents a novel class - F power amplifier for mobile applications in which with a proper harmonic tuning structure the need f or an extra fil tering section is eliminated . A class - F power a mplifier employing a GaN HEMT device has been designed, fabricated and measured at 900 MHz . The fabricated circuit achieves a n excel lent harmonic - suppression level and the t otal h armonic distortion is around 1.2% . It overcomes the narrow band performance of class - F power amplifier s, giving more than 70% efficiency over a 100 MHz bandwidth . Experimental results show that the amplifier is able to deliver 38.5 dBm output power while achieving the state - of - the - art PAE of 8 0.5 % with a peak drain eff iciency of 8 4 % , and a power gain of 13.6 dB for an input power of 25 dBm . A good agreement between measurement and simulation results is observed for the proposed structure.Peer ReviewedPostprint (published version

Large signal design of silicon field effect transistors for linear radio frequency power amplifiers

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