Efficient and Linear CMOS Power Amplifier and Front-end Design for Broadband Fully-Integrated 28-GHz 5G Phased Arrays

Demand for data traffic on mobile networks is growing exponentially with time and on a global scale. The emerging fifth-generation (5G) wireless standard is being developed with millimeter-wave (mm-Wave) links as a key technological enabler to address this growth by a 2020 time frame. The wireless industry is currently racing to deploy mm-Wave mobile services, especially in the 28-GHz band. Previous widely-held perceptions of fundamental propagation limitations were overcome using phased arrays. Equally important for success of 5G is the development of low-power, broadband user equipment (UE) radios in commercial-grade technologies. This dissertation demonstrates design methodologies and circuit techniques to tackle the critical challenge of key phased array front-end circuits in low-cost complementary metal oxide semiconductor (CMOS) technology. Two power amplifier (PA) proof-of-concept prototypes are implemented in deeply scaled 28- nm and 40-nm CMOS processes, demonstrating state-of-the-art linearity and efficiency for extremely broadband communication signals. Subsequently, the 40 nm PA design is successfully embedded into a low-power fully-integrated transmit-receive front-end module. The 28 nm PA prototype in this dissertation is the first reported linear, bulk CMOS PA targeting low-power 5G mobile UE integrated phased array transceivers. An optimization methodology is presented to maximizing power added efficiency (PAE) in the PA output stage at a desired error vector magnitude (EVM) and range to address challenging 5G uplink requirements. Then, a source degeneration inductor in the optimized output stage is shown to further enable its embedding into a two-stage transformer-coupled PA. The inductor helps by broadening inter-stage impedance matching bandwidth, and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured Pout/PAE at −25 dBc EVM for a 250 MHz-wide, 64-QAM orthogonal frequency division multiplexing (OFDM) signal with 9.6 dB peak-to-average power ratio (PAPR). The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6dB back-off from saturation. To the best of the author’s knowledge, these are the highest measured PAE values among published K- and K a-band CMOS PAs to date. To drastically extend the communication bandwidth in 28 GHz-band UE devices, and to explore the potential of CMOS technology for more demanding access point (AP) devices, the second PA is demonstrated in a 40 nm process. This design supports a signal radio frequency bandwidth (RFBW) >3× the state-of-the-art without degrading output power (i.e. range), PAE (i.e. battery life), or EVM (i.e. amplifier fidelity). The three-stage PA uses higher-order, dual-resonance transformer matching networks with bandwidths optimized for wideband linearity. Digital gain control of 9 dB range is integrated for phased array operation. The gain control is a needed functionality, but it is largely absent from reported high-performance mm-Wave PAs in the literature. The PA is fabricated in a 1P6M 40 nm CMOS LP technology with 1.1 V supply, and achieves Pout/PAE of +6.7 dBm/11% for an 8×100 MHz carrier aggregation 64-QAM OFDM signal with 9.7 dB PAPR. This PA therefore is the first to demonstrate the viability of CMOS technology to address even the very challenging 5G AP/downlink signal bandwidth requirement. Finally, leveraging the developed PA design methodologies and circuits, a low power transmit-receive phased array front-end module is fully integrated in 40 nm technology. In transmit-mode, the front-end maintains the excellent performance of the 40 nm PA: achieving +5.5 dBm/9% for the same 8×100 MHz carrier aggregation signal above. In receive-mode, a 5.5 dB noise figure (NF) and a minimum third-order input intercept point (IIP₃) of −13 dBm are achieved. The performance of the implemented CMOS frontend is comparable to state-of-the-art publications and commercial products that were very recently developed in silicon germanium (SiGe) technologies for 5G communication

Analysis and design on low-power multi-Gb/s serial links

High speed serial links are critical components for addressing the growing demand for I/O bandwidth in next-generation computing applications, such as many-core systems, backplane and optical data communications. Due to continued process scaling and circuit innovations, today's CMOS serial link transceivers can achieve tens of Gb/s per pin. However, most of their reported power efficiency improves much slower than the rise of data rate. Therefore, aggregate I/O power is increasing and will exceed the power budget if the trend for more off-chip bandwidth is sustained. In this work, a system level statistical analysis of serial links is first described, and compares the link performance of Non-Return-to-Zero (2-PAM) with higher-order modulation (duobinary) signaling schemes. This method enables fast and accurate BER distribution simulation of serial link transceivers that include channel and circuit imperfections, such as finite pulse rise/fall time, duty cycle variation, and both receiver and transmitter forwarded-clock jitter. Second, in order to address link power efficiency, two test chips have been implemented. The first one describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency, consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator coupled to a low-voltage swing, global clock distribution. Measurement results show a 6.4-7.2Gb/s data rate with BER < 10⁻¹² across 14 cm of PCB, and an 8Gb/s data rate through 4cm of PCB. Designed in a 1.2V, 90nm CMOS process, the ILRO achieves a wide tuning range from 1.6-2.6GHz. The total area of each receiver is 0.0174mm², resulting in a measured power efficiency of 0.6mW/Gb/s. Improving upon the first test chip, a second test chip for 8Gb/s forwarded clock serial link receivers exploits a low-power super-harmonic injection-locked ring oscillator for symmetric multi-phase local clock generation and deskewing. Further power reduction is achieved by designing most of the receiver circuits in the near-threshold region (0.6V supply), with the exception of only the global clock buffer, test buffers and synthesized digital test circuits at nominal 1V supply. At the architectural level, a 1:10 direct demultiplexing rate is chosen to achieve low supply operation by exploiting high-parallelism. Fabricated in 65nm CMOS technology, two receiver prototypes are integrated in this test chip, one without and the other with front-end boot-strapped S/Hs. Including the amortized power of global clock distribution, the proposed serial link receivers consume 1.3mW and 2mW respectively at 8Gb/s input data rate, achieving a power efficiency of 0.163mW/Gb/s and 0.25mW/Gb/s. Measurement results show both receivers achieve BER < 10⁻¹² across a 20-cm FR4 PCB channel

High-Efficiency Low-Voltage Rectifiers for Power Scavenging Systems

Abstract Rectifiers are commonly used in electrical energy conversion chains to transform the energy obtained from an AC signal source to a DC level. Conventional bridge and gate cross-coupled rectifier topologies are not sufficiently power efficient, particularly when input amplitudes are low. Depending on their rectifying element, their power efficiency is constrained by either the forward-bias voltage drop of a diode or the threshold voltage of a diode-connected MOS transistor. Advanced passive rectifiers use threshold cancellation techniques to effectively reduce the threshold voltage of MOS diodes. Active rectifiers use active circuits to control the conduction angle of low-loss MOS switches. In this thesis, an active rectifier with a gate cross-coupled topology is proposed, which replaces the diode-connected MOS transistors of a conventional rectifier with low-loss MOS switches. Using the inherent characteristics of MOS transistors as comparators, dynamic biasing of the bulks of main switches and small pull-up transistors, the proposed self-supplied active rectifier exhibits smaller voltage drop across the main switches leading to a higher power efficiency compared to conventional rectifier structures for a wide range of operating frequencies in the MHz range. Delivery of high load currents is another feature of the proposed rectifier. Using the bootstrapping technique, single- and double-reservoir based rectifiers are proposed. They present higher power and voltage conversion efficiencies compared to conventional rectifier structures. With a source amplitude of 3.3 V, when compared to the gate cross-coupled topology, the proposed active rectifier offers power and voltage conversion efficiencies improved by up to 10% and 16% respectively. The proposed rectifier using the bootstrap technique, including double- and single-reservoir schemes, are well suited for very low input amplitudes. They present power and voltage conversion efficiencies of 75% and 76% at input amplitude of 1.0 V and maintain their high efficiencies over input amplitudes greater than 1.0V. Single-reservoir bootstrap rectifier also reduces die area by 70% compared to its double-reservoir counterpart.---------Résumé Les redresseurs sont couramment utilisés dans de nombreux systèmes afin de transformer l'énergie électrique obtenue à partir d'une source alternative en une alimentation continue. Les topologies traditionnelles telles que les ponts de diodes et les redresseurs se servant de transistors à grilles croisées-couplées ne sont pas suffisamment efficaces en terme d’énergie, en particulier pour des signaux à faibles amplitudes. Dépendamment de leur élément de redressement, leur efficacité en termes de consommation d’énergie est limitée soit par la chute de tension de polarisation directe d'une diode, soit par la tension de seuil du transistor MOS. Les redresseurs passifs avancés utilisent une technique de conception pour réduire la tension de seuil des diodes MOS. Les redresseurs actifs utilisent des circuits actifs pour contrôler l'angle de conduction des commutateurs MOS à faible perte. Dans cette thèse, nous avons proposé un redresseur actif avec une topologie en grille croisée-couplée. Elle utilise des commutateurs MOS à faible perte à la place des transistors MOS connectés en diode comme redresseurs. Le circuit proposé utilise: des caractéristiques intrinsèques des transistors MOS pour les montages comparateurs et une polarisation dynamique des substrats des commutateurs principaux supportés par de petits transistors de rappel. Le redresseur proposé présente des faibles chutes de tension à travers le commutateur principal menant à une efficacité de puissance plus élevée par rapport aux structures d’un redresseur conventionnel pour une large gamme de fréquences de fonctionnement de l’ordre des MHz. La conduction des courants de charge élevée est une autre caractéristique du redresseur proposé. En utilisant la méthode de bootstrap, des redresseurs à simple et à double réservoir sont proposés. Ils présentent une efficacité de puissance et un rapport de conversion de tension élevés en comparaison avec les structures des redresseurs conventionnels. Avec une amplitude de source de 3,3 V, le redresseur proposé offre des efficacités de puissance et de conversion de tension améliorées par rapport au circuit à transistors croisés couplés. Ces améliorations atteignent 10% et 16% respectivement. Les redresseurs proposés utilisent la technique de bootstrap. Ils sont bien adaptés pour des amplitudes d'entrée très basses. À une amplitude d'entrée de 1,0 V, ces derniers redresseurs présentent des rendements de conversion de puissance et de tension de 75% et 76%. Le redresseur à simple réservoir réduit également l’aire de silicium requise de 70% par rapport à la version à double-réservoir

Wideband CMOS Data Converters for Linear and Efficient mmWave Transmitters

With continuously increasing demands for wireless connectivity, higher\ua0carrier frequencies and wider bandwidths are explored. To overcome a limited transmit power at these higher carrier frequencies, multiple\ua0input multiple output (MIMO) systems, with a large number of transmitters\ua0and antennas, are used to direct the transmitted power towards\ua0the user. With a large transmitter count, each individual transmitter\ua0needs to be small and allow for tight integration with digital circuits. In\ua0addition, modern communication standards require linear transmitters,\ua0making linearity an important factor in the transmitter design.In this thesis, radio frequency digital-to-analog converter (RF-DAC)-based transmitters are explored. They shift the transition from digital\ua0to analog closer to the antennas, performing both digital-to-analog\ua0conversion and up-conversion in a single block. To reduce the need for\ua0computationally costly digital predistortion (DPD), a linear and wellbehaved\ua0RF-DAC transfer characteristic is desirable. The combination\ua0of non-overlapping local oscillator (LO) signals and an expanding segmented\ua0non-linear RF-DAC scaling is evaluated as a way to linearize\ua0the transmitter. This linearization concept has been studied both for\ua0the linearization of the RF-DAC itself and for the joint linearization of\ua0the cascaded RF-DAC-based modulator and power amplifier (PA) combination.\ua0To adapt the linearization, observation receivers are needed.\ua0In these, high-speed analog-to-digital converters (ADCs) have a central\ua0role. A high-speed ADC has been designed and evaluated to understand\ua0how concepts used to increase the sample rate affect the dynamic performance

On-Chip Analog Circuit Design Using Built-In Self-Test and an Integrated Multi-Dimensional Optimization Platform

Nowadays, the rapid development of system-on-chip (SoC) market introduces tremendous complexity into the integrated circuit (IC) design. Meanwhile, the IC fabrication process is scaling down to allow higher density of integration but makes the chips more sensitive to the process-voltage-temperature (PVT) variations. A successful IC product not only imposes great pressure on the IC designers, who have to handle wider variations and enforce more design margins, but also challenges the test procedure, leading to more check points and longer test time. To relax the designers’ burden and reduce the cost of testing, it is valuable to make the IC chips able to test and tune itself to some extent. In this dissertation, a fully integrated in-situ design validation and optimization (VO) hardware for analog circuits is proposed. It implements in-situ built-in self-test (BIST) techniques for analog circuits. Based on the data collected from BIST, the error between the measured and the desired performance of the target circuit is evaluated using a cost function. A digital multi-dimensional optimization engine is implemented to adaptively adjust the analog circuit parameters, seeking the minimum value of the cost function and achieving the desired performance. To verify this concept, study cases of a 2nd/4th active-RC band-pass filter (BPF) and a 2nd order Gm-C BPF, as well as all BIST and optimization blocks, are adopted on-chip. Apart from the VO system, several improved BIST techniques are also proposed in this dissertation. A single-tone sinusoidal waveform generator based on a finite-impulse-response (FIR) architecture, which utilizes an optimization algorithm to enhance its spur free dynamic range (SFDR), is proposed. It achieves an SFDR of 59 to 70 dBc from 150 to 850 MHz after the optimization procedure. A low-distortion current-steering two-tone sinusoidal signal synthesizer based on a mixing-FIR architecture is also proposed. The two-tone synthesizer extends the FIR architecture to two stages and implements an up-conversion mixer to generate the two tones, achieving better than -68 dBc IM3 below 480 MHz LO frequency without calibration. Moreover, an on-chip RF receiver linearity BIST methodology for continuous and discrete-time hybrid baseband chain is proposed. The proposed receiver chain implements a charge-domain FIR filter to notch the two excitation signals but expose the third order intermodulation (IM3) tones. It simplifies the linearity measurement procedure–using a power detector is enough to analyze the receiver’s linearity. Finally, a low cost fully digital built-in analog tester for linear-time-invariant (LTI) analog blocks is proposed. It adopts a time-to-digital converter (TDC) to measure the delays corresponded to a ramp excitation signal and is able to estimate the pole or zero locations of a low-pass LTI system

Design of miniaturized radio-frequency DC-DC power converters

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 321-325).Power electronics appear in nearly every piece of modern electronic hardware, forming an essential conduit from electrical source to load. Portable electronics, an area where a premium is placed on size, weight, and cost, are driving the development of power systems with greater density and better manufacturability. This motivates a push to higher switching frequencies enabling smaller passive components and better integration. To realize these goals this thesis explores devices, circuits, and passives capable of operating efficiently into the VHF regime (30-300 MHz) and their integration into power electronic systems of high power density. A good integrated power MOSFET presages high-density converters. Previous VHF systems were demonstrated with bulky and expensive RF Lateral, Double-Diffused MOSFETs (LDMOSFET). We show that through a combination of layout optimization and safe operating area (SOA) extension integrated devices can achieve near-parity performance to their purpose-built RF discrete cousins over the desired operating regime. A layout optimization method demonstrating a 2x reduction in device loss is presented alongside experimental demonstration of SOA extension. Together the methods yield a 3x reduction in loss that bolsters the utility of the typical (and relatively inexpensive) LDMOS IC power process for VHF converters. Passive component synthesis is addressed in the context of an isolated VHF converter topology. We present a VHF topology where most of the magnetic energy storage is accomplished in a transformer that forms an essential part of the resonant network. The reduced component count aids in manufacturability and size, but places difficult requirements on the transformer design. An algorithm for synthesizing small and efficient air-core transformers with a fully-constrained inductance matrix is presented. Planar PCB transformers are fabricated and match the the design specifications to within 15%. They are 94% efficient and have a power density greater than 2kW per cubic inch. To take full advantage of good devices and printed passives, we develop an IC for the isolated converter having optimized power devices, and integrated gate driver, controller, and hotel functions. The chip is assembled into a complete converter system using the transformers and circuits described above. Flip-chip mounting is used to overcome bondwire parasitics, and reduce packaging volume. The final system achieves 75% efficiency at 75 MHz at 6W.by Anthony D. Sagneri.Ph.D

ULTRA LOW POWER CIRCUITS FOR WEARABLE BIOMEDICAL SENSORS

Ph.DDOCTOR OF PHILOSOPH

Electronic/electric technology benefits study

The benefits and payoffs of advanced electronic/electric technologies were investigated for three types of aircraft. The technologies, evaluated in each of the three airplanes, included advanced flight controls, advanced secondary power, advanced avionic complements, new cockpit displays, and advanced air traffic control techniques. For the advanced flight controls, the near term considered relaxed static stability (RSS) with mechanical backup. The far term considered an advanced fly by wire system for a longitudinally unstable airplane. In the case of the secondary power systems, trades were made in two steps: in the near term, engine bleed was eliminated; in the far term bleed air, air plus hydraulics were eliminated. Using three commercial aircraft, in the 150, 350, and 700 passenger range, the technology value and pay-offs were quantified, with emphasis on the fiscal benefits. Weight reductions deriving from fuel saving and other system improvements were identified and the weight savings were cycled for their impact on TOGW (takeoff gross weight) and upon the performance of the airframes/engines. Maintenance, reliability, and logistic support were the other criteria