Energy Neutral Activity Monitoring:Wearables Powered by Smart Inductive Charging Surfaces

Wearable technologies play a key role in the shift of traditional healthcare services towards eHealth and self-monitoring. Maintenance overheads, such as regular battery recharging, impose a limitation on the applicability of such technologies in some groups of the population. In this paper, we propose an activity monitoring system that is based on wearable sensors that are powered by textile inductive charging surfaces. By strategically positioning these surfaces on pieces of furniture that are routinely used, the system passively charges the wearable sensor whilst the user is present. As a proof-of-concept example, experiments conducted on a prototype implementation of the system suggest that 36 minutes of daily desktop computer usage are on average sufficient to maintain a wearable sensor energy neutral

High-performance long NoC link using delay-insensitive current-mode signaling

High-performance long-range NoC link enables efficient implementation of network-on-chip topologies which inherently require high-performance long-distance point-to-point communication such as torus and fat-tree structures. In addition, the performance of other topologies, such as mesh, can be improved by using high-performance link between few selected remote nodes.We presented novel implementation of high-performance long-range NoC link based onmultilevel current-mode signaling and delayinsensitive two-phase 1-of-4 encoding. Current-mode signaling reduces the communication latency of long wires significantlycompared to voltage-mode signaling, making it possible to achieve high throughput without pipelining and/or using repeaters. The performance of the proposed multilevel current-mode interconnect is analyzed and compared with two reference voltage mode interconnects. These two reference interconnects are designed using two-phase 1-of-4 encoded voltage-mode signaling, one with pipeline stages and the other using optimal repeater insertion. The proposed multilevel current-mode interconnect achieves higher throughput and lower latency than the two reference interconnects. Its throughput at 8mm wire length is 1.222GWord/swhich is 1.58 and 1.89 times higher than the pipelined and optimal repeater insertion interconnects, respectively. Furthermore, its power consumption is less than the optimal repeater insertion voltage-mode interconnect, at 10mm wire length its power consumption is 0.75mW while the reference repeater insertion interconnect is 1.066 mW. The effect of crosstalk is analyzed using four-bit parallel data transfer with the best-case and worst-case switching patterns and a transmission line model which has both capacitive coupling and inductive coupling.</p

Delay Extraction Based Equivalent Elmore Model For RLC On-Chip Interconnects

As feature sizes for VLSI technology is shrinking, associated with higher operating frequency, signal integrity analysis of on-chip interconnects has become a real challenge for circuit designers. For this purpose, computer-aided-design (CAD) tools are necessary to simulate signal propagation of on-chip interconnects which has been an active area for research. Although SPICE models exist which can accurately predict signal degradation of interconnects, they are computationally expensive. As a result, more effective and analytic models for interconnects are required to capture the response at the output of high speed VLSI circuits. This thesis contributes to the development of efficient and closed form solution models for signal integrity analysis of on-chip interconnects. The proposed model uses a delay extraction algorithm to improve the accuracy of two-pole Elmore based models used in the analysis of on-chip distributed RLC interconnects. In the proposed scheme, the time of fight signal delay is extracted without increasing the number of poles or affecting the stability of the transfer function. This algorithm is used for both unit step and ramp inputs. From the delay rational approximation of the transfer function, analytic fitted expressions are obtained for the 50% delay and rise time for unit step input. The proposed algorithm is tested on point to point interconnections and tree structure networks. Numerical examples illustrate improved 50% delay and rise time estimates when compared to traditional Elmore based two-pole models

Design and Optimization of Efficient Wireless Power Transfer Links for Implantable Biotelemetry Systems

Wireless power transmission is a technique that converts energy from radio frequency (RF) electromagnetic (EM) waves into DC voltage, which has been used here for the purpose of providing a power supply to bio–implantable batteryless sensors. The main constraints of the design are to achieve the minimum power required by the application, by still keeping the implant size small enough for the living subject’s body. Resonance–based inductive coupling is a method being actively researched for the use in this type of power transmission, which uses two pairs of inductor coils in the external and implant circuits. In this work, we have employed the resonance–based inductive coupling technique in order to develop a design and optimization procedure for the inductors. We have designed two systems with different configurations, and have achieved power transfer efficiencies of around 80% at a coil distance of 50mm for both systems. We have also optimized the power delivered to the load (implant) and developed a power harvesting unit. Misalignment issues due to the subject’s movements have been modeled for calculating the worst–case alignment, and finite element modeling of the inductors has been performed

Design and modelling of variability tolerant on-chip communication structures for future high performance system on chip designs

The incessant technology scaling has enabled the integration of functionally complex System-on-Chip (SoC) designs with a large number of heterogeneous systems on a single chip. The processing elements on these chips are integrated through on-chip communication structures which provide the infrastructure necessary for the exchange of data and control signals, while meeting the strenuous physical and design constraints. The use of vast amounts of on chip communications will be central to future designs where variability is an inherent characteristic. For this reason, in this thesis we investigate the performance and variability tolerance of typical on-chip communication structures. Understanding of the relationship between variability and communication is paramount for the designers; i.e. to devise new methods and techniques for designing performance and power efficient communication circuits in the forefront of challenges presented by deep sub-micron (DSM) technologies. The initial part of this work investigates the impact of device variability due to Random Dopant Fluctuations (RDF) on the timing characteristics of basic communication elements. The characterization data so obtained can be used to estimate the performance and failure probability of simple links through the methodology proposed in this work. For the Statistical Static Timing Analysis (SSTA) of larger circuits, a method for accurate estimation of the probability density functions of different circuit parameters is proposed. Moreover, its significance on pipelined circuits is highlighted. Power and area are one of the most important design metrics for any integrated circuit (IC) design. This thesis emphasises the consideration of communication reliability while optimizing for power and area. A methodology has been proposed for the simultaneous optimization of performance, area, power and delay variability for a repeater inserted interconnect. Similarly for multi-bit parallel links, bandwidth driven optimizations have also been performed. Power and area efficient semi-serial links, less vulnerable to delay variations than the corresponding fully parallel links are introduced. Furthermore, due to technology scaling, the coupling noise between the link lines has become an important issue. With ever decreasing supply voltages, and the corresponding reduction in noise margins, severe challenges are introduced for performing timing verification in the presence of variability. For this reason an accurate model for crosstalk noise in an interconnection as a function of time and skew is introduced in this work. This model can be used for the identification of skew condition that gives maximum delay noise, and also for efficient design verification

Design Considerations of Capacitive Power Transfer Systems

Capacitive power transfer (CPT) is a near-field wireless power transfer (WPT) technology that has attracted attention in different charging applications. By utilizing electric fields, CPT gives charging systems advantages in terms of cost, weight, flexibility, and mobility. This paper surveys a number of empirical published works in a period between 2015 and 2023. Additionally, it discusses theoretical and practical design considerations of a CPT system to understand and improve the technology and its applications. The paper studies the one- and two-port measuring approaches using vector network analyzers to determine the coupling parameters and compares the measurements to the simulated values using COMSOL Multiphysics ©. The two-port approach gives more accurate results than the one-port approach. The paper designs and tests a 13.56MHz CPT system using the two-port measurement results. The system transfers 100W at 87.4% efficiency and 30mm separation distance. Lastly, the paper discusses the design limitations and challenges of the CPT systems, aiming to emphasize the design obstacles that can drive the advancement of the CPT systems for wireless charging applications