Computer-Aided Modeling and Analysis of Power Processing Systems (CAMAPPS), phase 1

The large-signal behaviors of a regulator depend largely on the type of power circuit topology and control. Thus, for maximum flexibility, it is best to develop models for each functional block a independent modules. A regulator can then be configured by collecting appropriate pre-defined modules for each functional block. In order to complete the component model generation for a comprehensive spacecraft power system, the following modules were developed: solar array switching unit and control; shunt regulators; and battery discharger. The capability of each module is demonstrated using a simplified Direct Energy Transfer (DET) system. Large-signal behaviors of solar array power systems were analyzed. Stability of the solar array system operating points with a nonlinear load is analyzed. The state-plane analysis illustrates trajectories of the system operating point under various conditions. Stability and transient responses of the system operating near the solar array's maximum power point are also analyzed. The solar array system mode of operation is described using the DET spacecraft power system. The DET system is simulated for various operating conditions. Transfer of the software program CAMAPPS (Computer Aided Modeling and Analysis of Power Processing Systems) to NASA/GSFC (Goddard Space Flight Center) was accomplished

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

A Hybrid Method of Performing Electric Power System Fault Ride-Through Evaluations on Medium Voltage Multi-Megawatt Devices

This dissertation explores the design and analysis of a Hybrid Method of performing electrical power system fault ride-through evaluations on multi-megawatt, medium voltage power conversion equipment. Fault ride-through evaluations on such equipment are needed in order to verify and validate full scale designs prior to being implemented in the field. Ultimately, these evaluations will help in reducing the deployment risks associated with bringing new technologies into the marketplace. This is especially true for renewable energy and utility scale energy storage systems, where a significant amount of attention in recent years has focused on their ever increasing role in power system security and stability. The Hybrid Method couples two existing technologies together - a reactive voltage divider network and a power electronic variable voltage source - in order to overcome the inherent limitation of both methods, namely the short circuit duty required for implementation. This work provides the background of this limitation with respect to the existing technologies and demonstrates that the Hybrid Method can minimize the fault duty required for fault evaluations. The physical system, control objectives, and operation cycle of the Hybrid Method are analyzed with respect to the overall objective of reducing the fault duty of the system. A vector controller is designed to incorporate the time variant nature of the Hybrid Method operation cycle, limit the fault current seen by the power electronic variable voltage source, and provide regulation of the voltage at the point of common coupling with the device being evaluated. In order to verify the operation of both the Hybrid Method physical system and vector controller, a controller hardware-in-the-loop experiment is created in order to simulate the physical system in real-time against the prototype implementation of the vector controller. The physical system is simulated in a Real Time Digital Simulator and is controlled with the Hybrid Method vector controller implemented on a National Instruments FPGA. In order to evaluate the complete performance of the Hybrid Method, both a synchronous generator and a doubly-fed induction generator are modeled as the device under test in the simulations of the physical system. Finally, the results of the controller hardware-in-the-loop experiments are presented which demonstrate that the Hybrid Method is a viable solution to performing fault ride-through evaluations on multi-megawatt, medium voltage power conversion equipment

Wireless Power Transfer Techniques for Implantable Medical Devices:A Review

Wireless power transfer (WPT) systems have become increasingly suitable solutions for the electrical powering of advanced multifunctional micro-electronic devices such as those found in current biomedical implants. The design and implementation of high power transfer efficiency WPT systems are, however, challenging. The size of the WPT system, the separation distance between the outside environment and location of the implanted medical device inside the body, the operating frequency and tissue safety due to power dissipation are key parameters to consider in the design of WPT systems. This article provides a systematic review of the wide range of WPT systems that have been investigated over the last two decades to improve overall system performance. The various strategies implemented to transfer wireless power in implantable medical devices (IMDs) were reviewed, which includes capacitive coupling, inductive coupling, magnetic resonance coupling and, more recently, acoustic and optical powering methods. The strengths and limitations of all these techniques are benchmarked against each other and particular emphasis is placed on comparing the implanted receiver size, the WPT distance, power transfer efficiency and tissue safety presented by the resulting systems. Necessary improvements and trends of each WPT techniques are also indicated per specific IMD

Flexible Receivers in CMOS for Wireless Communication

Consumers are pushing for higher data rates to support more services that are introduced in mobile applications. As an example, a few years ago video-on-demand was only accessed through landlines, but today wireless devices are frequently used to stream video. To support this, more flexible network solutions have merged in 4G, introducing new technical problems to the mobile terminal. New techniques are thus needed, and this dissertation explores five different ideas for receiver front-ends, that are cost-efficient and flexible both in performance and operating frequency. All ideas have been implemented in chips fabricated in 65 nm CMOS technology and verified by measurements. Paper I explores a voltage-mode receiver front-end where sub-threshold positive feedback transistors are introduced to increase the linearity in combination with a bootstrapped passive mixer. Paper II builds on the idea of 8-phase harmonic rejection, but simplifies it to a 6-phase solution that can reject noise and interferers at the 3rd order harmonic of the local oscillator frequency. This provides a good trade-off between the traditional quadrature mixer and the 8- phase harmonic rejection mixer. Furthermore, a very compact inductor-less low noise amplifier is introduced. Paper III investigates the use of global negative feedback in a receiver front-end, and also introduces an auxiliary path that can cancel noise from the main path. In paper IV, another global feedback based receiver front-end is designed, but with positive feedback instead of negative. By introducing global positive feedback, the resistance of the transistors in a passive mixer-first receiver front-end can be reduced to achieve a lower noise figure, while still maintaining input matching. Finally, paper V introduces a full receiver chain with a single-ended to differential LNA, current-mode downconversion mixers, and a baseband circuity that merges the functionalities of the transimpedance amplifier, channel-select filter, and analog-to-digital converter into one single power-efficient block