Special purpose parallel computer architecture for real-time control and simulation in robotic applications

This is a real-time robotic controller and simulator which is a MIMD-SIMD parallel architecture for interfacing with an external host computer and providing a high degree of parallelism in computations for robotic control and simulation. It includes a host processor for receiving instructions from the external host computer and for transmitting answers to the external host computer. There are a plurality of SIMD microprocessors, each SIMD processor being a SIMD parallel processor capable of exploiting fine grain parallelism and further being able to operate asynchronously to form a MIMD architecture. Each SIMD processor comprises a SIMD architecture capable of performing two matrix-vector operations in parallel while fully exploiting parallelism in each operation. There is a system bus connecting the host processor to the plurality of SIMD microprocessors and a common clock providing a continuous sequence of clock pulses. There is also a ring structure interconnecting the plurality of SIMD microprocessors and connected to the clock for providing the clock pulses to the SIMD microprocessors and for providing a path for the flow of data and instructions between the SIMD microprocessors. The host processor includes logic for controlling the RRCS by interpreting instructions sent by the external host computer, decomposing the instructions into a series of computations to be performed by the SIMD microprocessors, using the system bus to distribute associated data among the SIMD microprocessors, and initiating activity of the SIMD microprocessors to perform the computations on the data by procedure call

Chaos in computer performance

Modern computer microprocessors are composed of hundreds of millions of transistors that interact through intricate protocols. Their performance during program execution may be highly variable and present aperiodic oscillations. In this paper, we apply current nonlinear time series analysis techniques to the performances of modern microprocessors during the execution of prototypical programs. Our results present pieces of evidence strongly supporting that the high variability of the performance dynamics during the execution of several programs display low-dimensional deterministic chaos, with sensitivity to initial conditions comparable to textbook models. Taken together, these results show that the instantaneous performances of modern microprocessors constitute a complex (or at least complicated) system and would benefit from analysis with modern tools of nonlinear and complexity science

Kilo-instruction processors: overcoming the memory wall

Historically, advances in integrated circuit technology have driven improvements in processor microarchitecture and led to todays microprocessors with sophisticated pipelines operating at very high clock frequencies. However, performance improvements achievable by high-frequency microprocessors have become seriously limited by main-memory access latencies because main-memory speeds have improved at a much slower pace than microprocessor speeds. Its crucial to deal with this performance disparity, commonly known as the memory wall, to enable future high-frequency microprocessors to achieve their performance potential. To overcome the memory wall, we propose kilo-instruction processors-superscalar processors that can maintain a thousand or more simultaneous in-flight instructions. Doing so means designing key hardware structures so that the processor can satisfy the high resource requirements without significantly decreasing processor efficiency or increasing energy consumption.Peer ReviewedPostprint (published version

Daily weather direct readout microprocessor study

The work completed included a study of the requirements and hardware and software implementation techniques for NIMBUS ESMR and TWERLE direct readout applications using microprocessors. Many microprocessors were studied for this application. Because of the available Interdata development capabilities, it was concluded that future implementations be on an Interdata microprocessor which was found adequate for the task

CMOS design of cellular APAPs and FPAPAPs: an overview

CNN-based analog visual microprocessors have similarities with the so-called Single Instruction Multiple Data systems, although they work directly on analog signal representations obtained through embedded optical sensors and hence do not need a frontend sensory plane or analog-to-digital converters. The architecture of these visual microprocessors is illustrated in the paper through two prototype chips, namely: ACE4K and ACE16K. In both cases, as in other related chips the architecture includes a core array of interconnected elementary processing units, surrounded by a global circuitry.Office of Naval Research N00014-00-10429Comisión Interministerial de Ciencia y Tecnología TIC-1999-082

Shoe-box orbit determination system for SMM preliminary results

The implementation of both sequential and batch methods of estimation on IMP-16 microprocessors was investigated. Simulated data was used from a tracking and data relay satellite whose target satellite was the Solar Maximum Mission. An interesting feature of the hardware was the use of two interconnected IMP-16's. Some preliminary results from the study, as well as the difficulties and advantages in the use of microprocessors, are presented

An assembler for the MOS Technology 6502 microprocessor as implemented in jolt (TM) and KIM-1 (TM)

Design of low-cost, microcomputer-based navigation receivers, and the assembler are described. The development of computer software for microprocessors is materially aided by the assembler program using mnemonic variable names. The flexibility of the environment provided by the IBM's Virtual Machine Facility and the Conversational Monitor System, make possible the convenient assembler access. The implementation of the assembler for the microprocessor chip serves a part of the present need and forms a model for support of other microprocessors

A command and data subsystem for deep space exploration based on the RCA 1802 microprocessor in a distributed configuration

The Command and Data Subsystem (CDS) is an RCA 1802microprocessor based subsystem that acts as the central nervous system for the Galileo Orbiter Spacecraft. All communication between the ground and spacecraft flows through the CDS. The CDS also distributes commands in real time, algorithmetrically expanded from a data base loaded from the ground and in response to spacecraft alarms. The distributed microprocessor system is configured as a redundant set of hardware with three microprocessors on each half. The microprocessors are surrounded by a group of special purpose hardware components which greatly enhance the ability of the software to perform its task. It is shown how the software architecture makes a distributed system of six microprocessors appear to each user as a single virtual machine, and collectively as a set of cooperating virtual machines that prevent the simultaneous presence of the several users from interfering destructively with each other

Microprogramming and microprocessors in the Netherlands

This paper gives a short survey of the activities in the field of microprocessors and microprogramming in the Netherlands. In the first part of it the activies within the Universities and non commercial institutes are mentioned. The second part deals with the industrial activity. The author is aware of the incompleteness of the survey. The reason for it is twofold. First; Some of the activies, especially in the industrie, have confidential aspects. The information may not yet appear in a paper like this. Second; He is not aware of all activities carried out in the field. A list of names of the institutes etcand eventual contactpersons is included. A literature list is not added, because not much literature is available now