Modulo scheduling for a fully-distributed clustered VLIW architecture

Clustering is an approach that many microprocessors are adopting in recent times in order to mitigate the increasing penalties of wire delays. We propose a novel clustered VLIW architecture which has all its resources partitioned among clusters, including the cache memory. A modulo scheduling scheme for this architecture is also proposed. This algorithm takes into account both register and memory inter-cluster communications so that the final schedule results in a cluster assignment that favors cluster locality in cache references and register accesses. It has been evaluated for both 2- and 4-cluster configurations and for differing numbers and latencies of inter-cluster buses. The proposed algorithm produces schedules with very low communication requirements and outperforms previous cluster-oriented schedulers.Peer ReviewedPostprint (published version

ARTIFICIAL NEURAL NETWORKS AND THEIR APPLICATIONS IN BUSINESS

In modern software implementations of artificial neural networks the approach inspired by biology has more or less been abandoned for a more practical approach based on statistics and signal processing. In some of these systems, neural networks, or parts of neural networks (such as artificial neurons), are used as components in larger systems that combine both adaptive and non-adaptive elements. There are many problems which are solved with neural networks, especially in business and economic domains.neuron, neural networks, artificial intelligence, feed-forward neural networks, classification

A coprocessor design for the architectural support of non-numeric operations

Computer Science is concerned with the electronic manipulation of information. Continually increasing amounts of computer time are being expended on information that is not numeric. This is represented in part by modem computing requirements such as the block moves associated with context switching and virtual memory management, peripheral device communication, compilers, editors, word processors, databases, and text retrieval. This dissertation examines the traditional support of non-numeric information from a software, firmware, and hardware perspective and presents a coprocessor design to improve the performance of a set of non-numeric operations. Simple micro-coding of operations can provide a degree of performance improvement through parallel execution of instructions and control store access speeds. New special purpose parallel hardware algorithms can yield complexity improvements. This dissertation presents a parallel hardware regular expression searching algorithm which requires linear time and quadratic space compared to software uniprocessor algorithms which require exponential time and space. A very large scale integration (VLSD implementation of a version of this algorithm was designed, fabricated, and tested. The hardware. searching algorithm is then combined with other special purpose hardware to implement a set of operations. Simulation is then used to quantify the performance improvement of the operations when compared to software solutions. A coprocessor approach allows the optional addition of hardware to accelerate a set of operations. This is appropriate from a complex instruction set computer (CISC) perspective since hardware acceleration is being utilized. It is also appropriate from a reduced instruction set computer (RISC) perspective since the operations are distributed away from the central processing unit (CPU)

Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA

This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard) algorithm and describes the design and performance testing algorithm for embedded system. Also, with the spread of reconfigurable hardware such as FPGAs (Field Programmable Gate Array) embedded cryptographic hardware became cost-effective. Nevertheless, it is worthy to note that nowadays, even hardwired cryptographic algorithms are not so safe. From another side, the self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. Hardware acceleration significantly increases the performance of embedded systems built on programmable logic. Allowing a FPGA-based MicroBlaze processor to self-select the coprocessors uses can help reduce area requirements and increase a system's versatility. The architecture proposed in this paper is an optimal hardware implementation algorithm and takes dynamic partially reconfigurable of FPGA. This implementation is good solution to preserve confidentiality and accessibility to the information in the numeric communication

STANDARDS IN CONTROL AND PROTECTION TEHNOLOGY FOR ELECTRIC POWER SYSTEMS

The features of the standard IEC 16850 with respect to intelligent applications in substations are summarized. It is shown how modeling of functions independently from its allocation to devices allows optimizing existing applications and opening up for future intelligent applications. The data model provides all information in a substation needed not only for control and protection functions but also about the IEDs and the switchgear configuration.electric power systems

STANDARDS IN CONTROL AND PROTECTION TEHNOLOGY FOR ELECTRIC POWER SYSTEMS

The features of the standard IEC 16850 with respect to intelligent applications in substations are summarized. It is shown how modeling of functions independently from its allocation to devices allows optimizing existing applications and opening up for future intelligent applications. The data model provides all information in a substation needed not only for control and protection functions but also about the IEDs and the switchgear configuration.electric power system

Format Based Data Compression

Working Paper Serie

Count three for wear able computers

This paper is a postprint of a paper submitted to and accepted for publication in the Proceedings of the IEE Eurowearable 2003 Conference, and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at the IET Digital Library. A revised version of this paper was also published in Electronics Systems and Software, also subject to Institution of Engineering and Technology Copyright. The copy of record is also available at the IET Digital Library.A description of 'ubiquitous computer' is presented. Ubiquitous computers imply portable computers embedded into everyday objects, which would replace personal computers. Ubiquitous computers can be mapped into a three-tier scheme, differentiated by processor performance and flexibility of function. The power consumption of mobile devices is one of the most important design considerations. The size of a wearable system is often a design limitation

Architecture and Hardware Solutions Symbolic Information Processing

The failure of some national projects AXES to expected results. According to experts one of the reasons is the lack of adequate theoretical apparatus for generating high-branching processes, unjustified detraction of opportunities enumerative models representative of AXES, which have their own laws paralleling computing, can not be reduced to algorithmic rules. This fact determines the need to develop innovative approaches to problem solving and organization of AXES interrelated levels of system design symbolic computation, from the linguistic level to the appropriate software and appropriate hardware level