309 research outputs found
Design of Asynchronous Processor
There has been a resurgence of interest in asynchronous design recently. The renewed interest in asynchronous design results from its potential to address the problem faced by the synchronous design methodology. In asynchronous
methodology, there is no global clock controlling the synchronization of a circuit; instead, the data communication between each functional unit is completed through local request-acknowledge handshake protocol. The growth in demand of high performance portable systems has accelerated asynchronous logic design technique which can offers better performance and lower power consumption especially in the development of the asynchronous processor for mobile and portable application. In this thesis, the design and verification of an 8-bit asynchronous pipelined
processor is presented. The developed asynchronous processor is based on Harvard architecture and uses Reduced Instruction Set Computer (RISC) instruction set architecture. 24 instructions are supported by the processor including register, memory, branch and jump operations. The processor has three-stage pipelining i.e.
fetch, decode and execution pipeline. Micropipelines framework with 2-phase signalling protocol and bundled-data approach is employed in designing complex and powerful asynchronous control circuits for the processor. Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used to design and construct all parts of the asynchronous processor. Simulation, synthesis and verification of the processor are carried out using MAX +PLUS II software. The simulation results have demonstrated that the developed 8-bit asynchronous RISC processor is working correctly using current Field Programmable Gate Array (FPGA) technology. This processor employed 903 logic cells and has 6144 memory bits for instruction and data memory. Each of the processor subsystem can operates at different cycle time, thus enable an asynchronous processor achieving 11.95MHz average speed performance
Some unusual micropipeline circuits
Journal ArticleWe present a few unusual Micropipelines (Sutherland, CACM, September 1989) that employ the Muller C-ELEMENT or an extension of the C-ELEMENT called LOCKC (Liebchen and Gopalakrishnan, ICCD, 1992). We first describe two variations of the two-dimensional Micropipeline structure realized using ordinary C-ELEMENTs. These micropipelines can be used to control wavefront arrays (S.-Y.Kung et.al, IEEE Computer, 1987). Next, we present a ring style arbiter realized using a LocKC-based one-dimensional micropipeline. Finally, we present a solution to the symmetric crossbar arbitration problem posed by Tamir and Chi (IEEE Trans. Parallel and Dist Systems, Jan '93) using a circuit that employs the two-dimensional micropipeline as well as the LOCKC. We present various circuits to solve the symmetric crossbar arbitration problem, including ones that consume very little power when idling
Testing micropipelines
Journal ArticleMicropipelines, self-timed event-driven pipelines, are an attractive way of structuring asynchronous systems that exhibit many of the advantages of general asynchronous systems, but enough structure to make the design of significant systems practical. As with any design method, testing is critical. We present a technique for testing self-timed micropipelines for stuck-at faults and for delay faults an the bundled data paths by modifying the latch and control elements to include a built-in scan path for testing. This scan path allows the processing logic in the micropipeline, to be fully tested with only a small overhead in the latch and control circuits. The test method is very similar to scan testing in synchronous systems, but the micropipeline retains its self-timed behavior during normal operation
Implementación de Circuitos Self-Timed de 2 y 4 Fases en FPGAs
Versión electrónica de la ponencia presentada en Jornadas de Computación Reconfigurable y Aplicaciones, celebrado en Madrid en 2003Aunque los dispositivos programables tipo FPGAs están diseñados para la
implementación eficiente de circuitos síncronos, en la actualidad constituyen la única
opción disponible para prototipado rápido de circuitos self-timed. En este artículo se
presentan algunas ideas para el diseño de estos circuitos en FPGAs, para dos principales
protocolo: 2 y 4 fases. Como caso de estudio, se ha elegido la multiplicación binaria.
Se ilustra el funcionamiento de estos circuitos y se realiza una comparación entre
las dos opciones de sincronización. También se resumen los principales resultados en
área, velocidad, retardo de pistas y fanout. Como marco tecnológico se utiliza una
FPGA Xilinx Virtex II
Fred: an architecture for a self-timed decoupled computer
Journal ArticleDecoupled computer architectures provide an effective means of exploiting instruction level parallelism. Self-timed micropipeline systems are inherently decoupled due to the elastic nature of the basic FIFO structure, and may be ideally suited for constructing decoupled computer architectures. Fred is a self-timed decoupled, pipelined computer architecture based on micropipelines. We present the architecture of Fred, with specific details on a micropipelined implementation that includes support for multiple functional units and out-of- order instruction completion due to the self-timed decoupling
Unfaithful Glitch Propagation in Existing Binary Circuit Models
We show that no existing continuous-time, binary value-domain model for
digital circuits is able to correctly capture glitch propagation. Prominent
examples of such models are based on pure delay channels (P), inertial delay
channels (I), or the elaborate PID channels proposed by Bellido-D\'iaz et al.
We accomplish our goal by considering the solvability/non-solvability border of
a simple problem called Short-Pulse Filtration (SPF), which is closely related
to arbitration and synchronization. On one hand, we prove that SPF is solvable
in bounded time in any such model that provides channels with non-constant
delay, like I and PID. This is in opposition to the impossibility of solving
bounded SPF in real (physical) circuit models. On the other hand, for binary
circuit models with constant-delay channels, we prove that SPF cannot be solved
even in unbounded time; again in opposition to physical circuit models.
Consequently, indeed none of the binary value-domain models proposed so far
(and that we are aware of) faithfully captures glitch propagation of real
circuits. We finally show that these modeling mismatches do not hold for the
weaker eventual SPF problem.Comment: 23 pages, 15 figure
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