TAMTAMS: a flexible and open tool for UDSM process-to-system design space exploration

Ultra Deep Sub-Micron (UDSM) processes, as well as beyond CMOS technology choices, influence circuits performance with a chain of consequences through devices, circuits and systems that are difficult to predict. Nonetheless effective design-space exploration enables process optimization and early design organization. We introduce TAMTAMS, a tool based on an open, flexible and simple structure, which allows to predict system level features starting from technology variables. It is modular and based on a clear dependency tree of modules, each related to a model of specific quantities (e.g. device currents, circuit delay, interconnects noise, ....) presented in literature. Models can be compared and sensitivity to parameters observed. We believe our contribution gives a fresh point of view on process-to-system predictors. Though still in development, it already shows flexibility and allows a traceable path of a technology parameter on its way to the system level

Тенденции развития технологии вычислительной техники

Представлены закономерности и тенденции развития технологии вычислительной техники, современные предложения в рамках импортозамещения по созданию отечественных высокопроизводительных гетерогенных вычислительных платформ с процессорными модулями разной архитектуры, сформулированы предложения в сфере реализации высоких технологи

Integrated Application of Active Controls (IAAC) technology to an advanced subsonic transport project: Current and advanced act control system definition study. Volume 2: Appendices

The current status of the Active Controls Technology (ACT) for the advanced subsonic transport project is investigated through analysis of the systems technical data. Control systems technologies under examination include computerized reliability analysis, pitch axis fly by wire actuator, flaperon actuation system design trade study, control law synthesis and analysis, flutter mode control and gust load alleviation analysis, and implementation of alternative ACT systems. Extensive analysis of the computer techniques involved in each system is included

High density circuit technology, part 3

Dry processing - both etching and deposition - and present/future trends in semiconductor technology are discussed. In addition to a description of the basic apparatus, terminology, advantages, glow discharge phenomena, gas-surface chemistries, and key operational parameters for both dry etching and plasma deposition processes, a comprehensive survey of dry processing equipment (via vendor listing) is also included. The following topics are also discussed: fine-line photolithography, low-temperature processing, packaging for dense VLSI die, the role of integrated optics, and VLSI and technology innovations

Heat transfer studies of a flow-through module for electronics cooling

The thermal performance characteristics of an electronics cooling Liquid Flow Through Module (FTM) were experimentally investigated. Different sets of experiments were conducted for each side of the FTM. A synthetic dielectric polyalphaolefin type coolant, Brayco Micronic 889, was used. Six etched foil type heaters were attached to one side of the FTM over the fluid flow path while three heaters were attached to the other side of the module. Inlet and outlet fluid temperatures as well as surface temperature data were acquired from both sides of the module for several different flow rate and power setting combinations to quantify the effectiveness of the FTM. Correlations, in terms of Reynolds and Stanton numbers were formulated according to the data for both sides of the module.http://archive.org/details/heattransferstud109457599Turkish Navy author

1997-1999-UNM CATALOG

Course catalog for 1997-1999https://digitalrepository.unm.edu/course_catalogs/1097/thumbnail.jp

MODEL DEVELOPMENT FOR MICRO–CHANNEL COOLING TECHNOLOGY

The micro–channel research literature presents a clear need to provide accurate models that can predict pressure drop and heat transfer coefficients for a greater number of experimental data sets while capturing the physical phenomena of various flow patterns associated with the onset of nucleate boiling in the two–phase region. The model approach developed have been evaluated for the purpose of facilitating an efficient design instrument for micro–channels to predict the pressure drop related to heat input for the single phase through to the boiling [two–phase] region as well as heat transfer coefficient calculations for a single micro–channel. The simplified homogeneous model provides a lower bound for pressure drop estimates and the weighted annular–homogeneous model produces an upper bound value. Input parameters include the micro–channel dimensions, fluid flow rate, inlet temperature, thermo–physical properties of the respected fluid, and outlet pressure. Polynomial correlations for water are obtained from curve–fitting data available from the 1997 Ashrae Handbook over the temperature range of 0.01 to 200 ºC for the thermodynamic properties that include liquid density, viscosity, thermal conductivity, specific heat capacity and change of enthalpy [latent heat of vapourization]. The model results are evaluated over four independent experimental data sets that are available in the literature to demonstrate the sufficient accuracy for channel dimensions ranging from 50 µm to 713 µm. The independent data sets were numerically reproduced from figures presented in the research literature. The boiling front, pressure drop, heat transfer coefficient, wall temperature profile and vapour quality characteristics are evaluated. Heat transfer coefficient calculations were made via the Kandlikar correlation and the Kandlikar enhancement factor method that is corrected for vapour quality. The model produced pressure drop results that were within about a 30% error to the experimental data sets evaluated for heat fluxes in the range of 50 W/cm² to values exceeding 150 W/cm². Heat transfer coefficient values calculated between the two correlations of Kandlikar were within an estimated error of 30% to experimental measurements and demonstrated results in the two–phase region that exceeded 110 000 W/cm² K

Caractérisation et modélisation électrique de substrats SOI avancés

Silicon-on-insulator (SOI) substrates represent the best solution to achieve high performance devices. Electrical characterization methods are required to monitor the material quality before full transistor fabrication. The classical configuration used for SOI measurements is the pseudo-MOSFET. In this thesis, we focused on the enrichment of techniques in Ψ-MOSFET for the characterization of bare SOI and III-V wafers. The experimental setup for static ID-VG was improved using a vacuum contact for the back gate, increasing the measurement stability. Furthermore, this contact proved to be critical for achieving correct capacitance values with split-CV and quasi-static techniques (QSCV). We addressed the possibility to extract Dit values from split-CV and we demonstrated by modeling that it is impossible in typical sized SOI samples because of the time constant associated to the channel formation. The limitation was solved performing QSCV measurements. Dit signature was experimentally evidenced and physically described. Several SOI structures (thick and ultra-thin silicon films and BOX) were characterized. In case of passivated samples, the QSCV is mostly sensitive to the silicon film-BOX interface. In non-passivated wafers, a large defect related peak appears at constant energy value, independently of the film thickness; it is associated to the native oxide present on the silicon surface. For low-frequency noise measurements, a physical model proved that the signal arises from localized regions surrounding the source and drain contacts.Les substrats Silicium-sur-Isolant (SOI) représentent la meilleure solution pour obtenir des dispositifs microélectroniques ayant de hautes performances. Des méthodes de caractérisation électrique sont nécessaires pour contrôler la qualité SOI avant la réalisation complète de transistors. La configuration classique utilisée pour les mesures du SOI est le pseudo-MOFSET. Dans cette thèse, nous nous concentrons sur l'amélioration des techniques autour du Ψ-MOFSET, pour la caractérisation des plaques SOI et III-V. Le protocole expérimental de mesures statiques ID-VG a été amélioré par l'utilisation d'un contact par le vide en face arrière, permettant ainsi d'augmenter la stabilité des mesures. De plus, il a été prouvé que ce contact est essentiel pour obtenir des valeurs correctes de capacité avec les méthodes split-CV et quasi-statique. L'extraction des valeurs de Dit avec split-CV a été explorée, et un model physique nous a permis de démontrer que ceci n'est pas possible pour des échantillons SOI typiquement utilisés, à cause de la constante de temps reliée à la formation du canal. Cette limitation a été résolue un effectuant des mesures de capacité quasi-statique (QSCV). La signature des Dit a été mise en évidence expérimentalement et expliquée physiquement. Dans le cas d'échantillons passivés, les mesures QSCV sont plus sensibles à l'interface silicium-BOX. Pour les échantillons non passivés, un grand pic dû à des défauts d'interface apparait pour des valeurs d'énergie bien identifiées et correspondant aux défauts à l'interface film de silicium-oxyde natif. Nous présentons des mesures de bruit à basses fréquences, ainsi qu'un model physique démontrant que le signal émerge de régions localisées autour des contacts source et drain

Microchannel integration for forced heat removal on 2D and 3D chips

En microélectronique, plusieurs tendances telles que l'empilement 3D et l'amincissement de puces amènent des défis thermiques grandissants. Ces défis sont exacerbés lorsqu'appliqués aux appareils mobiles où l'espace et la puissance disponibles pour le refroidissement sont limités. Le but de cette thèse est de développer des outils de conception et méthodes d'implémentation de microcanaux pour le refroidissement microfluidique de puces 2D et 3D avec points chauds destinés aux appareils mobiles.Une méthode de conception pour optimiser la configuration des microcanaux refroidissant une puce est développée utilisant un plan d'expériences numériques. La configuration optimisée propose le refroidissement à une température maximale de 89 °C d'un point chaud de 2 W par un écoulement où la perte de charge est plus petit que 1 kPa. Des prototypes avec différents empilements et distributions de microcanaux sont fabriqués par gravure profonde et apposés par pick-and-place. Un banc de caractérisation et une puce thermique test sont fabriqués pour caractériser expérimentalement les prototypes de refroidissement avec différentes configurations. Un prototype avec microcanaux limités aux alentours des points chauds et reportés sur la face arrière de la puce test atteint une résistance thermique de 2.8 °C/W. Cela est réalisé avec un débit de 9.4 ml/min et des pertes de charges de 19.2 kPa, soit une puissance hydraulique de 3 mW. Ce refroidissement extrait 7.3 W générés sur un seul serpentin à un flux thermique de 1 185 W/cm² pour un coefficient de performance de 2 430. Les résultats de l'optimisation suggèrent que la dissipation thermique soit exploitée en ajoutant des microcanaux en parallèle, plutôt qu'en allongeant les microcanaux. On observe expérimentalement comme numériquement que la résistance liée à la hausse de température du fluide domine la résistance totale. Enfin, il apparaît que les différents empilements ont un effet plus important sur la résistance thermique que les distributions de microcanaux dans les plages observées.In microelectronics, trends such as 3D stacking and die thinning bring major thermal challenges. Those challenges are exacerbated when applied to mobile devices where the available space and power for cooling are limited. This thesis aims at developing design tools and implementation techniques for microchannels cooling on 2D and 3D chips with hot spots for mobile devices. A design technique to optimize the microchannel configuration for chip cooling is developed using numerical experimentation plans. The optimized configuration suggests a cooling configuration reaching a maximum temperature of 89 °C on a 2 W hot spot, using a flow at a pressure drop plus petit que 1 kPa. Prototypes with different stacking and microchannel distributions are fabricated using deep reactive ion etching process and stacked using pick-and-place technique. A characterization bench and a thermal test chip are fabricated for experimental characterization of the cooling prototypes from various configurations. A prototype with microchannel zones limited to the hot spot vicinity and installed on the backside of the test chip reached a thermal resistance of 2.8 °C/W. This performance is achieved using a flow rate of 9.4 ml/min with a pressure drop of 19.2 kPa, representing a hydraulic power of 3 mW. Such cooling removes 7.3 W generated on a single heat source, representing a heat flux of 1 185 W/cm² for a coefficient of performance of 2 430. The optimization results suggest that the heat spreading is better exploited using parallel microchannels, rather than lengthen microchannels. It is both observed experimentally and numerically that the thermal resistance related to the fluid temperature rise is the major contribution to the total thermal resistance. Finally, it appears that the different stacking effects on thermal resistance are more important than the microchannels distributions in the observed ranges