Thermo-mechanical analysis of flexible and stretchable systems

This paper presents a summary of the modeling and technology developed for flexible and stretchable electronics. The integration of ultra thin dies at package level, with thickness in the range of 20 to 30 μ m, into flexible and/or stretchable materials are demonstrated as well as the design and reliability test of stretchable metal interconnections at board level are analyzed by both experiments and finite element modeling. These technologies can achieve mechanically bendable and stretchable subsystems. The base substrate used for the fabrication of flexible circuits is a uniform polyimide layer, while silicones materials are preferred for the stretchable circuits. The method developed for chip embedding and interconnections is named Ultra Thin Chip Package (UTCP). Extensions of this technology can be achieved by stacking and embedding thin dies in polyimide, providing large benefits in electrical performance and still allowing some mechanical flexibility. These flexible circuits can be converted into stretchable circuits by replacing the relatively rigid polyimide by a soft and elastic silicone material. We have shown through finite element modeling and experimental validation that an appropriate thermo mechanical design is necessary to achieve mechanically reliable circuits and thermally optimized packages

Using Micro-Raman Spectroscopy to Assess MEMS Si/SiO2 Membranes Exhibiting Negative Spring Constant Behavior

We introduce a novel micro-mechanical structure that exhibits two regions of stable linear positive and negative stiffness. Springs, cantilevers, beams and any other geometry that display an increasing return force that is proportional to the displacement can be considered to have a “Hookean” positive spring constant, or stiffness. Less well known is the opposite characteristic of a reducing return force for a given deflection, or negative stiffness. Unfortunately many simple negative stiffness structures exhibit unstable buckling and require additional moving components during deflection to avoid deforming out of its useful shape. In Micro-Electro-Mechanical Systems (MEMS) devices, buckling caused by stress at the interface of silicon and thermally grown SiO2 causes tensile and compressive forces that will warp structures if the silicon layer is thin enough. The 1 mm2 membrane structures presented here utilizes this effect but overcome this limitation and empirically demonstrates linearity in both regions. The Si/SiO2 membranes presented deflect ~17 μm from their pre-released position. The load deflection curves produced exhibit positive linear stiffness with an inflection point holding nearly constant with a slight negative stiffness. Depositing a 0.05 μm titanium and 0.3 μm layer of gold on top of the Si/SiO2 membrane reduces the initial deflection to ~13.5 μm. However, the load deflection curve produced illustrates both a linear positive and negative spring constant with a fairly sharp inflection point. These results are potentially useful to selectively tune the spring constant of mechanical structures used in MEMS. The structures presented are manufactured using typical micromachining techniques and can be fabricated in-situ with other MEMS devices

Pathway to the PiezoElectronic Transduction Logic Device

The information age challenges computer technology to process an exponentially increasing computational load on a limited energy budget - a requirement that demands an exponential reduction in energy per operation. In digital logic circuits, the switching energy of present FET devices is intimately connected with the switching voltage, and can no longer be lowered sufficiently, limiting the ability of current technology to address the challenge. Quantum computing offers a leap forward in capability, but a clear advantage requires algorithms presently developed for only a small set of applications. Therefore, a new, general purpose, classical technology based on a different paradigm is needed to meet the ever increasing demand for data processing.Comment: in Nano Letters (2015

Ultra-Stretchable Interconnects for High-Density Stretchable Electronics

The exciting field of stretchable electronics (SE) promises numerous novel applications, particularly in-body and medical diagnostics devices. However, future advanced SE miniature devices will require high-density, extremely stretchable interconnects with micron-scale footprints, which calls for proven standardized (complementary metal-oxide semiconductor (CMOS)-type) process recipes using bulk integrated circuit (IC) microfabrication tools and fine-pitch photolithography patterning. Here, we address this combined challenge of microfabrication with extreme stretchability for high-density SE devices by introducing CMOS-enabled, free-standing, miniaturized interconnect structures that fully exploit their 3D kinematic freedom through an interplay of buckling, torsion, and bending to maximize stretchability. Integration with standard CMOS-type batch processing is assured by utilizing the Flex-to-Rigid (F2R) post-processing technology to make the back-end-of-line interconnect structures free-standing, thus enabling the routine microfabrication of highly-stretchable interconnects. The performance and reproducibility of these free-standing structures is promising: an elastic stretch beyond 2000% and ultimate (plastic) stretch beyond 3000%, with 10 million cycles at 1000% stretch with <1% resistance change. This generic technology provides a new route to exciting highly-stretchable miniature devices.Comment: 13 pages, 5 figure, journal publicatio

Reduced-Order Modelling of the Bending of an Array of Torsional Micromirrors

Reduced-Order Modelling of the Bending of an Array of An array of micromirrors for beam steering optical switching has been designed in a thick polysilicon technology. A novel semi-analytical method to calculate the static characteristics of the micromirrors by taking into account the flexural deformation of the structure is presented. The results are compared with 3D coupled-field FEM simulation.Comment: Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions

Technical Design Report for the PANDA Micro Vertex Detector

This document illustrates the technical layout and the expected performance of the Micro Vertex Detector (MVD) of the PANDA experiment. The MVD will detect charged particles as close as possible to the interaction zone. Design criteria and the optimisation process as well as the technical solutions chosen are discussed and the results of this process are subjected to extensive Monte Carlo physics studies. The route towards realisation of the detector is outlined

An SU-8 Microgripper Based on the Cascaded V-Shaped Electrothermal Actuators: Design, Fabrication, Simulation and Experimental Investigations

This chapter presents the design, fabrication, numerical simulations and experimental investigations of a polymeric microgripper designed using the cascaded V-shaped electrothermal actuators. The microgripper has a total length around 1 mm and a total thickness of only 20 μm. The microgripper was simulated using electro-thermo-mechanical finite element method (FEM) in order to check the performance of the gripper. As structural material of the microgripper, the SU-8 biocompatible polymer was used during the fabrication process. A fabrication process was implemented to realize the microgripper using a symmetrically sandwich structure. The metallic micro-heaters were encapsulated in the polymeric actuation structure of the microgrippers to reduce the undesirable out-of-plane displacement of the gripper tips and the mechanical stress, to improve the thermal efficiency, and for obtaining the electrical isolation of the structure. Experimental testing has been performed to determine the openings and the temperatures of the microgripper tips as function of electrical current. A displacement of the tips of more than 50 μm can be obtained at an electrical current of around 26–28 mA. A comparison between the simulation results and the measurements were also presented

Reliability analysis of foil substrate based integration of silicon chips

Flexible electronics has attracted significant attention in the recent past due to the booming wearables market in addition to the ever-increasing interest for faster, thinner and foldable mobile phones. Ultra-thin bare silicon ICs fabricated by thinning down standard ICs to thickness below 50 μm are flexible and therefore they can be integrated on or in polymer foils to create flexible hybrid electronic (FHE) components that could be used to replace rigid standard surface mount device (SMD) components. The fabricated FHE components referred as chip foil packages (CFPs) in this work are ideal candidates for FHE system integration owing to their ability to deliver high performance at low power consumption while being mechanically flexible. However, very limited information is available in the literature regarding the reliability of CFPs under static and dynamic bending. The lack of such vital information is a major obstacle impeding their commercialization. With the aim of addressing this issue, this thesis investigates the static and dynamic bending reliability of CFPs. In this scope, the static bending reliability of CFPs has been investigated in this thesis using flexural bending tests by measuring their fracture strength. Then, Finite Element Method (FEM) simulations have been implemented to calculate the fracture stress of ultra-thin flexible silicon chips where analytical formulas may not be applied. After calculating the fracture stress from FEM simulations, the enhancement in robustness of ultra-thin chips (UTCs) against external load has also been proved and quantified with further experimental investigations. Besides, FEM simulations have also been used to analyse the effect of Young’s Modulus of embedding materials on the robustness of the embedded UTCs. Furthermore, embedding the UTCs in polymer layers has also been experimentally proven to be an effective solution to reduce the influence of thinning and dicing induced damages on the robustness of the embedded UTCs. Traditional interconnection techniques such as wire bonding may not be implemented to interconnect ultra-thin silicon ICs owing to the high mechanical forces involved in the processes that would crack the chips. Therefore, two novel interconnection methods namely (i) flip-chip bonding with Anisotropic Conductive Adhesive (ACA) and (ii) face-up direct metal interconnection have been implemented in this thesis to interconnect ultra-thin silicon ICs to the corresponding interposer patterns on foil substrates. The CFP samples thus fabricated were then used for the dynamic bending reliability investigations. A custom-built test equipment was developed to facilitate the dynamic bending reliability investigations of CFPs. Experimental investigations revealed that the failure of CFPs under dynamic bending was caused mainly by the cracking of the redistribution layer (RDL) interconnecting the chip and the foil. Furthermore, it has also been shown that the CFPs are more vulnerable to repeated compressive bending than to repeated tensile bending. Then, the influence of dimensional factors such as the thickness of the chip as well as the RDL on the dynamic bending reliability of CFPs have also been studied. Upon identifying the plausible cause behind the cracking of the RDL leading to the failure of the CFPs, two methods to improve the dynamic bending reliability of the RDL have been suggested and demonstrated with experimental investigations. The experimental investigations presented in this thesis adds some essential information to the state-of-the-art concerning the static and the dynamic bending reliability of UTCs integrated in polymer foils that are not yet available in the literature and aids to establish in-depth knowledge of mechanical reliability of the components required for manufacturing future FHE systems. The strategies devised to enhance the robustness of UTCs and CFPs could serve as guidelines for fabricating reliable FHE components and systems