Microcomputer Based Simulation

Digital simulation is a useful tool in many scientific areas. Interactive simulation can provide the user with a better appreciation of a problem area. With the introduction of large scale integrated circuits and in particular the advent of the microprocessor, a large amount of computing power is available at low cost. The aim of this project therefore was to investigate the feasibility of producing a minimum cost, easy to use, interactive digital simulation system. A hardware microcomputer system was constructed to test simulation program concepts and an interactive program was designed and developed for this system. By the use of a set of commands and subsequent interactive dialogue, the program allows the user to enter and perform simulation tasks. The simulation program is unusual in that it does not require a sophisticated operating system or other system programs such as compilers. The program does not require any backup memory devices such as magnetic disc or tape and indeed could be stored in ROM or EPROM. The program is designed to be flexible and extendable and could be easily modified to run with a variety of hardware configurations. The highly interactive nature of the system means that its operation requires very little programming experience. The microcomputer hardware system uses two microprocessors together with specially designed interfaces. One was dedicated to the implementation of the simulation equations, and the other provided an input/output capability including a low cost CRT display

Design of a LAPD interface using the T7130 multichannel LAPD controller and the T715A synchronous protocol data formatter

As the ISDN telecommunications standard gains acceptance, there is an ever increasing need for intelligent interfaces to implement the L2 protocol known as LAPD. The T7130 MLC, the T7115A SPYDER-T and the MC68020 microprocessor were used to design a LAPD Interface that conforms to the LAPD protocol as specified by CCITT. The LAPD Interface utilizes a Shared Memory Array which is attached to the Data Link Processors in a single bus configuration. The SMA Arbitration Control allows access to the SMA on a prioritized basis and was implemented as a state machine using PAL\u27s. L2 drivers and L3 management software were written and used to test the operability of the interface via an emulator. The LAPD Interface was able to terminate 32 I-IDLC channels configured for LAPD operation with an average throughput of 942.42 messages per second. The LAPD Interface was also able to operate efficiently in an environment in which random errors of the order of 1E-6 were injected

Proceedings of the NASA Conference on Space Telerobotics, volume 4

Papers presented at the NASA Conference on Space Telerobotics are compiled. The theme of the conference was man-machine collaboration in space. The conference provided a forum for researchers and engineers to exchange ideas on the research and development required for the application of telerobotic technology to the space systems planned for the 1990's and beyond. Volume 4 contains papers related to the following subject areas: manipulator control; telemanipulation; flight experiments (systems and simulators); sensor-based planning; robot kinematics, dynamics, and control; robot task planning and assembly; and research activities at the NASA Langley Research Center

Aeronautical Engineering: A continuing bibliography (supplement 158)

This bibliography lists 499 reports, articles and other documents introduced into the NASA scientific and technical information system in January 1983

Comparing Innovation Performance in the EU and the USA: Lessons from Three ICT Sub-Sectors

The objective of the study is to document the existence of innovation gaps between the EU and its main competitors in specific ICT sub-sectors – namely web services, industrial robotics and display technologies –and to explore the role of government policies in Europe’s future needs for innovation in information and communication technologies (ICT) through a comparison with the USA and Asian countries. Our analysis shows that rather than there being a simple innovation gap with the EU lagging behind the USA, a more nuanced picture emerges in which firms in different countries have strengths in different sub-sectors and in different parts of the value chain. A key lesson from the analysis of the three subsectors is the critical importance of higher education, particularly elite university research, and of local networks as generated by clusters. Governments can also encourage innovation through appropriate intellectual property and competition laws and, more generally, through the development of a business environment conducive to innovation. Finally, Governments can have a very important role through the funding of early-stage innovationJRC.J.3-Information Societ

Studies of inspection algorithms and associated microprogrammable hardware implementations

This work is concerned with the design and development of real-time algorithms for industrial inspection applications. Rather than implement algorithms in dedicated hardware, microprogrammable machines were considered essential in order to maintain flexibility. After a survey of image pattern recognition where algorithms applicable to real-time use are cited, this thesis presents industrial inspection algorithms that locate and scrutinise actual manufactured products. These are fast and robust - a necessary requirement in industrial environments. The National Physical Laboratory have developed a Linear Array Processor (LAP) specifically designed for industrial recognition work. As with most array processors, the LAP has a greater performance than conventional processors, yet is strictly limited to parallel algorithms for optimum performance. It was therefore necessary to incorporate sequentialism into the design of a multiprocessor system. A microcoded bit-slice Sequential Image Processor (SIP) has been designed and built at RHBNC in conjunction with the NPL. This was primarily intended as a post-processor for the LAP based on the VMEbus but in fact has proved its usefulness as a stand-alone processor. This is described along with an assembler written for SIP which translates assembly language mnemonics to microcode. This work, which includes a review of current architectures, leads to the specification of a hybrid (SIMD/NIMD) architecture consisting of multiple autonomous sequential processors. This involves an analysis of various configurations and entails an investigation of the source of bottlenecks within each design. Such systems require a significant amount of interprocessor communication: methods for achieving this are discussed, some of which have only become practical with the decrease incost of electronic components. This eventually leads to a system for which algorithm execution speed increases approximately linearly with the number of processors. The algorithms described in earlier chapters are examined on the system and the practicalities of such a design are analysed in detail. Overall, this thesis has arrived at designs of programmable real-time inspection systems, and has obtained guidelines which will help with the implementation of future inspection systems.<p