Utilizing Unconventional CMOS Techniques for Low Voltage Low Power Analog Circuits Design for Biomedical Applications

Tato disertační práce se zabývá navržením nízkonapěťových, nízkopříkonových analogových obvodů, které používají nekonvenční techniky CMOS. Lékařská zařízení na bateriové napájení, jako systémy pro dlouhodobý fyziologický monitoring, přenosné systémy, implantovatelné systémy a systémy vhodné na nošení, musí být male a lehké. Kromě toho je nutné, aby byly tyto systémy vybaveny baterií s dlouhou životností. Z tohoto důvodu převládají v biomedicínských aplikacích tohoto typu nízkopříkonové integrované obvody. Nekonvenční techniky jako např. využití transistorů s řízeným substrátem (Bulk-Driven “BD”), s plovoucím hradlem (Floating-Gate “FG”), s kvazi plovoucím hradlem (Quasi-Floating-Gate “QFG”), s řízeným substrátem s plovoucím hradlem (Bulk-Driven Floating-Gate “BD-FG”) a s řízeným substrátem s kvazi plovoucím hradlem (Bulk-Driven Quasi-Floating-Gate “BD-QFG”), se v nedávné době ukázaly jako efektivní prostředek ke zjednodušení obvodového zapojení a ke snížení velikosti napájecího napětí směrem k prahovému napětí u tranzistorů MOS (MOST). V práci jsou podrobně představeny nejdůležitější charakteristiky nekonvenčních technik CMOS. Tyto techniky byly použity pro vytvoření nízko napěťových a nízko výkonových CMOS struktur u některých aktivních prvků, např. Operational Transconductance Amplifier (OTA) založené na BD, FG, QFG, a BD-QFG techniky; Tunable Transconductor založený na BD MOST; Current Conveyor Transconductance Amplifier (CCTA) založený na BD-QFG MOST; Z Copy-Current Controlled-Current Differencing Buffered Amplifier (ZC-CC-CDBA) založený na BD MOST; Winner Take All (WTA) and Loser Take All (LTA) založený na BD MOST; Fully Balanced Four-Terminal Floating Nullor (FBFTFN) založený na BD-QFG technice. Za účelem ověření funkčnosti výše zmíněných struktur, byly tyto struktury použity v několika aplikacích. Výkon navržených aktivních prvků a příkladech aplikací je ověřován prostřednictvím simulačních programů PSpice či Cadence za použití technologie 0.18 m CMOS.This doctoral thesis deals with designing ultra-low-voltage (LV) low-power (LP) analog circuits utilizing the unconventional CMOS techniques. Battery powered medical devices such as; long term physiological monitoring, portable, implantable, and wearable systems need to be small and lightweight. Besides, long life battery is essential need for these devices. Thus, low-power integrated circuits are always paramount in such biomedical applications. Recently, unconventional CMOS techniques i.e. Bulk-Driven (BD), Floating-Gate (FG), Quasi-Floating-Gate (QFG), Bulk-Driven Floating-Gate (BD-FG) and Bulk-Driven Quasi-Floating-Gate (BD-QFG) MOS transistors (MOSTs) have revealed as effective devices to reduce the circuit complexity and push the voltage supply of the circuit towards threshold voltage of the MOST. In this work, the most important features of the unconventional CMOS techniques are discussed in details. These techniques have been utilized to perform ultra-LV LP CMOS structures of several active elements i.e. Operational Transconductance Amplifier (OTA) based on BD, FG, QFG, and BD-QFG techniques; Tunable Transconductor based on BD MOST; Current Conveyor Transconductance Amplifier (CCTA) based on BD-QFG MOST; Z Copy-Current Controlled-Current Differencing Buffered Amplifier (ZC-CC-CDBA) based on BD MOST; Winner Take All (WTA) and Loser Take All (LTA) based on BD MOST; Fully Balanced Four-Terminal Floating Nullor (FBFTFN) based on BD-QFG technique. Moreover, to verify the workability of the proposed structures, they were employed in several applications. The performance of the proposed active elements and their applications were investigated through PSpice or Cadence simulation program using 0.18 m CMOS technology.

Efficient Dual Output Regulating Rectifier and Adiabatic Charge Pump for Biomedical Applications Employing Wireless Power Transfer †

A power management unit (PMU) is an essential block for diversified multi-functional low-power Internet of Things (IoT) and biomedical electronics. This paper includes a theoretical analysis of a high current, single-stage ac-dc, reconfigurable, dual output, regulating rectifier consisting of pulse width modulation (PWM) and pulse frequency modulation (PFM). The regulating rectifier provides two independently regulated supply voltages of 1.8 V and 3.3 V from an input ac voltage. The PFM control feedback consists of feedback-driven regulation to adjust the driving frequency of the power transistors through adaptive buffers in the active rectifier. The PWM/PFM mode control provides a feedback loop to adjust the conduction duration accurately and minimize power losses. The design also includes an adiabatic charge pump (CP) to provide a higher voltage level. The adiabatic CP consists of latch-up and power-saving topologies to enhance its power efficiency. Simulation results show that the dual regulating rectifier has 94.3% voltage conversion efficiency with an ac input magnitude of 3.5 Vp. The power conversion efficiency of the regulated 3.3 V output voltage is 82.3%. The adiabatic CP has an overall voltage conversion efficiency (VCE) of 92.9% with a total on-chip capacitance of 60 pF. The circuit was designed using 180 nm CMOS technology

Low Voltage Low Power Analogue Circuits Design

Disertační práce je zaměřena na výzkum nejběžnějších metod, které se využívají při návrhu analogových obvodů s využití nízkonapěťových (LV) a nízkopříkonových (LP) struktur. Tyto LV LP obvody mohou být vytvořeny díky vyspělým technologiím nebo také využitím pokročilých technik návrhu. Disertační práce se zabývá právě pokročilými technikami návrhu, především pak nekonvenčními. Mezi tyto techniky patří využití prvků s řízeným substrátem (bulk-driven - BD), s plovoucím hradlem (floating-gate - FG), s kvazi plovoucím hradlem (quasi-floating-gate - QFG), s řízeným substrátem s plovoucím hradlem (bulk-driven floating-gate - BD-FG) a s řízeným substrátem s kvazi plovoucím hradlem (quasi-floating-gate - BD-QFG). Práce je také orientována na možné způsoby implementace známých a moderních aktivních prvků pracujících v napěťovém, proudovém nebo mix-módu. Mezi tyto prvky lze začlenit zesilovače typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za účelem potvrzení funkčnosti a chování výše zmíněných struktur a prvků byly vytvořeny příklady aplikací, které simulují usměrňovací a induktanční vlastnosti diody, dále pak filtry dolní propusti, pásmové propusti a také univerzální filtry. Všechny aktivní prvky a příklady aplikací byly ověřeny pomocí PSpice simulací s využitím parametrů technologie 0,18 m TSMC CMOS. Pro ilustraci přesného a účinného chování struktur je v disertační práci zahrnuto velké množství simulačních výsledků.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the non–conventional ones which are bulk–driven (BD), floating–gate (FG), quasi–floating–gate (QFG), bulk–driven floating–gate (BD–FG) and bulk–driven quasi–floating–gate (BD–QFG) techniques. The thesis also looks at ways of implementing structures of well–known and modern active elements operating in voltage–, current–, and mixed–mode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fully–differential second generation current conveyor (FB–CCII), fully–balanced differential difference amplifier (FB–DDA), voltage differencing transconductance amplifier (VDTA), current–controlled current differencing buffered amplifier (CC–CDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diode–less rectifier and inductance simulations, as well as low–pass, band–pass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.

Dual Output Regulating Rectifier for an Implantable Neural Interface

This paper presents the design of a power management circuit consisting of a dual output regulating rectifier configuration featuring pulse width modulation (PWM) and pulse frequency modulation (PFM) to control the regulated output of 1.8 V, and 3.3 V from a single input ac voltage. The PFM control feedback consists of feedback-driven regulation to adjust the driving frequency of the power transistors through the buffers in the active rectifier. The PWM mode control provides a feedback loop to accurately adjust the conduction duration. The design also includes an adiabatic charge pump (CP) to power stimulators in an implantable neural interface. The adiabatic CP consists of latch up and power saving topologies to enhance its energy efficiency. Simulation results show that the dual regulating rectifier has 94.3% voltage conversion efficiency with an ac input magnitude of 3.5 Vp. The power transfer efficiency of the regulated 3.3 V output voltage is 82.3%. The dual output regulating rectifier topology is suitable for multi-functional implantable devices. The adiabatic CP has an overall efficiency of 92.9% with an overall on-chip capacitance of 60 pF. The circuit was designed in a 180-nm CMOS technology

Rectification, amplification and switching capabilities for energy harvesting systems: power management circuit for piezoelectric energy harvester

Dissertação de mestrado em Biomedical EngineeringA new energy mechanism needs to be addressed to overcome the battery dependency, and consequently extend Wireless Sensor Nodes (WSN) lifetime effectively. Energy Harvesting is a promising technology that can fulfill that premise. This work consists of the realization of circuit components employable in a management system for a piezoelectric-based energy harvester, with low power consumption and high efficiency. The implementation of energy harvesting systems is necessary to power-up front-end applications without any battery. The input power and voltage levels generated by the piezoelectric transducer are relatively low, especially in small-scale systems, as such extra care has to be taken in power consumption and efficiency of the circuits. The main contribution of this work is a system capable of amplifying, rectifying and switching the unstable signal from an energy harvester source. The circuit components are designed based on 0.13 Complementary Metal-Oxide-Semiconductor (CMOS) technology. An analog switch, capable of driving the harvesting circuit at a frequency between 1 and 1 , with proper temperature behaviour, is designed and verified. An OFF resistance of 520.6 Ω and isolation of −111.24 , grant excellent isolation to the circuit. The designed voltage amplifier is capable of amplifying a minor signal with a gain of 42.56 , while requiring low power consumption. The output signal is satisfactorily amplified with a reduced offset voltage of 8 . A new architecture of a two-stage active rectifier is proposed. The power conversion efficiency is 40.4%, with a voltage efficiency of up to 90%. Low power consumption of 17.7 is achieved by the rectifier, with the embedded comparator consuming 113.9 . The outcomes validate the circuit’s power demands, which can be used for other similar applications in biomedical, industrial, and commercial fields.Para combater a dependência dos dispositivos eletrónicos relativamente ás baterias é necessário um novo sistema energético, que permita prolongar o tempo de vida útil dos mesmos. Energy Harvesting é uma tecnologia promissora utilizada para alimentar dispositivos sem bateria. Este trabalho consiste na realização de componentes empregáveis num circuito global para extrair energia a partir ds vibrações de um piezoelétricos com baixo consumo de energia e alta eficiência. Os níveis de potência e voltagem gerados pelo transdutor piezoelétrico são relativamente baixos, especialmente em sistemas de pequena escala, por isso requerem cuidado extra relativamente ao consumo de energia e eficiência dos circuitos. A principal contribuição deste trabalho é um sistema apropriado para amplificar, retificar e alternar o sinal instável proveniente de uma fonte de energy harvesting. Os componentes do sistema são implementados com base na tecnologia CMOS com 0.13 . Um interruptor analógico capaz de modelar a frequência do sinal entre 1 e 1 e estável perante variações de temperatura, é implementado. O circuito tem um excelente isolamento de −111.24 , devido a uma resistência OFF de 520.6 Ω. O amplificador implementado é apto a amplificar um pequeno sinal com um ganho de 42.56 e baixo consumo. O sinal de saída é satisfatoriamente amplificado com uma voltagem de offset de 8 . Um retificador ativo de dois estágios com uma nova arquitetura é proposto. A eficiência de conversão de energia atinge os 40.4%, com uma eficiência de voltagem até 90%. O retificador consome pouca energia, apenas 17.7 , incorporando um comparador de 113.9 . Os resultados validam as exigências energéticas do circuito, que pode ser usado para outras aplicações similares no campo biomédico, industrial e comercial

Integrated circuit & system design for concurrent amperometric and potentiometric wireless electrochemical sensing

Complementary Metal-Oxide-Semiconductor (CMOS) biosensor platforms have steadily grown in healthcare and commerial applications. This technology has shown potential in the field of commercial wearable technology, where CMOS sensors aid the development of miniaturised sensors for an improved cost of production and response time. The possibility of utilising wireless power and data transmission techniques for CMOS also allows for the monolithic integration of the communication, power and sensing onto a single chip, which greatly simplifies the post-processing and improves the efficiency of data collection. The ability to concurrently utilise potentiometry and amperometry as an electrochemical technique is explored in this thesis. Potentiometry and amperometry are two of the most common transduction mechanisms for electrochemistry, with their own advantages and disadvantages. Concurrently applying both techniques will allow for real-time calibration of background pH and for improved accuracy of readings. To date, developing circuits for concurrently sensing potentiometry and amperometry has not been explored in the literature. This thesis investigates the possibility of utilising CMOS sensors for wireless potentiometric and amperometric electrochemical sensing. To start with, a review of potentiometry and amperometry is evaluated to understand the key factors behind their operation. A new configuration is proposed whereby the reference electrode for both electrochemistry techniques are shared. This configuration is then compared to both the original configurations to determine any differences in the sensing accuracy through a novel experiment that utilises hydrogen peroxide as a measurement analyte. The feasibility of the configuration with the shared reference electrode is proven and utilised as the basis of the electrochemical configuration for the front end circuits. A unique front-end circuit named DAPPER is developed for the shared reference electrode topology. A review of existing architectures for potentiometry and amperometry is evaluated, with a specific focus on low power consumption for wireless applications. In addition, both the electrochemical sensing outputs are mixed into a single output data channel for use with a near-field communication (NFC). This mixing technique is also further analysed in this thesis to understand the errors arising due to various factors. The system is fabricated on TSMC 180nm technology and consumes 28µW. It measures a linear input current range from 250pA - 0.1µW, and an input voltage range of 0.4V - 1V. This circuit is tested and verified for both electrical and electrochemical tests to showcase its feasibility for concurrent measurements. This thesis then provides the integration of wireless blocks into the system for wireless powering and data transmission. This is done through the design of a circuit named SPACEMAN that consists of the concurrent sensing front-end, wireless power blocks, data transmission, as well as a state machine that allows for the circuit to switch between modes: potentiometry only, amperometry only, concurrent sensing and none. The states are switched through re-booting the circuit. The core size of the electronics is 0.41mm² without the coil. The circuit’s wireless powering and data transmission is tested and verified through the use of an external transmitter and a connected printed circuit board (PCB) coil. Finally, the future direction for ongoing work to proceed towards a fully monolithic electrochemical technique is discussed through the next development of a fully integrated coil-on-CMOS system, on-chip electrodes with the electroplating and microfludics, the development of an external transmitter for powering the device and a test platform. The contributions of this thesis aim to formulate a use for wireless electrochemical sensors capable of concurrent measurements for use in wearable devices.Open Acces

Minimum component high frequency current mode rectifier

In this paper a current mode full wave rectifier circuit is proposed. The current mode rectifiercircuit is implemented utilizing a floating current source (FCS) as an active element. Theminimum component full wave rectifier utilizes only a single floating current source, twodiodes and two grounded resistors. The extremely simple implementation enjoys highfrequency operation and provides both inverting and non-inverting rectified outputssimultaneously. The rectifier system can work up to a frequency of 500MHz with acceptabledistortion. The circuit exhibits low power consumption at ±0.75V supply voltage. Thenon-ideal and temperature analysis was also performed to study their impact on itsperformance. It was also shown that FCS can work as half wave rectifier as well. Theperformance of the circuit is evaluated using 0.18μm TSMC CMOS parameters using Hspice.Keywords: current-mode circuits; floating current source; high frequency; rectifier